Information to the Project HD44780 Driver
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Information to the Project HD44780 Driver
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This project contains VHDL descriptions for driving a standard HD44780
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This project contains VHDL descriptions for driving a standard HD44780
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LCD Driver with a minimum of inputs. Please read on.
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LCD Driver with a minimum of inputs. Please read on.
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Information
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Information
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Author: J.E.J. op den Brouw
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Author: J.E.J. op den Brouw
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Company: De Haagse Hogeschool
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Company: De Haagse Hogeschool
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Rationale: This driver is written to facilitate my students
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Rationale: This driver is written to facilitate my students
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Software: Quartus II v11.1 / ModelSim v10.0.c / Windows 7
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Software: Quartus II v11.1 / ModelSim v10.0.c / Windows 7
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Hardware: Terasic DE0 board with optional display (Cyclone III)
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Hardware: Terasic DE0 board with optional display (Cyclone III)
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Status: Alpha, tested by my students.
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Status: Alpha, tested by my students.
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Files
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Files
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lcd_driver_hd44780_module.vhd - The Driver
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lcd_driver_hd44780_module.vhd - The Driver
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tb_lcd_driver_hd44780_module.vhd - Simple testbench
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tb_lcd_driver_hd44780_module.vhd - Simple testbench
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tb_lcd_driver_hd44780_module.do - ModelSim command file
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tb_lcd_driver_hd44780_module.do - ModelSim command file
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example_driver.vhd - Example on how to use the driver
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example_driver.vhd - Example on how to use the driver
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tb_example_driver.vhd - Simple testbench
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tb_example_driver.vhd - Simple testbench
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tb_example_driver.do - ModelSim command file
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tb_example_driver.do - ModelSim command file
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lcd_driver_hd44780.sdc - Synopsys Constraints File (clock info only)
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lcd_driver_hd44780.sdc - Synopsys Constraints File (clock info only)
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readme.txt - This file
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readme.txt - This file
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Overall Description
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Overall Description
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Currently, this driver uses the 8-bit databus mode. This is not a big problem
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Currently, this driver uses the 8-bit databus mode. This is not a big problem
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for most FPGA's because of the numerous pins.
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for most FPGA's because of the numerous pins.
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Please note that there are a lot of almost-the-same displays available, so
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Please note that there are a lot of almost-the-same displays available, so
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it's not guaranteed to work with all displays available. Also, timing may differ.
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it's not guaranteed to work with all displays available. Also, timing may differ.
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This code is tested on a Terasic DE0-board with an optional LCD display.
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This code is tested on a Terasic DE0-board with an optional LCD display.
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See the weblinks:
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See the weblinks:
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http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
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http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=56&No=364
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http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396
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http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=396
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for more info. The display used has only two lines.
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for more info. The display used has only two lines.
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The VHDL description can both be simulated and synthesized.
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The VHDL descriptions can both be simulated and synthesized.
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This driver has a User Side and a LCD Side. The user is to interface at the User Side
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This driver has a User Side and a LCD Side. The user is to interface at the User Side
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and has a number of "routines" at her disposal. The User Side implements the following
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and has a number of "routines" at her disposal. The User Side implements the following
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inputs/routines in order of priority:
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inputs/routines in order of priority:
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Command inputs:
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Command inputs:
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init: a logic 1 initializes the display
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init: a logic 1 initializes the display
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cls: a logic 1 clears the display (and goes to home)
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cls: a logic 1 clears the display (and goes to home)
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home: a logic 1 sets the cursor to row 0, column 0
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home: a logic 1 sets the cursor to row 0, column 0
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goto10: a logic 1 sets the cursor to row 1, column 0
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goto10: a logic 1 sets the cursor to row 1, column 0
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goto20: a logic 1 sets the cursor to row 2, column 0
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goto20: a logic 1 sets the cursor to row 2, column 0
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goto30: a logic 1 sets the cursor to row 3, column 0
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goto30: a logic 1 sets the cursor to row 3, column 0
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wr: a logic 1 writes a character to the display
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wr: a logic 1 writes a character to the display
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Data inputs:
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Data inputs:
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data: an 8-bit data to be written to the display
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data: an 8-bit data to be written to the display
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The user has one observable output:
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The user has one observable output:
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busy: a logic 1 indicates that the driver is currently
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busy: a logic 1 indicates that the driver is currently
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busy driving the display, a logic 0 indicates that
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busy driving the display, a logic 0 indicates that
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the driver waits for the next command.
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the driver waits for the next command.
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The user can supply the next generics, which are processed at
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The user can supply the next generics, which are processed at
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instantiation of the module:
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instantiation of the module:
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freq: the clock frequency at which the hardware has to run.
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freq: the clock frequency at which the hardware has to run.
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this frequency is mandatory because of internal delays
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this frequency is mandatory because of internal delays
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calculated, defaults to 50 MHz.
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calculated, defaults to 50 MHz.
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areset_pol:
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areset_pol:
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the polarity of the reset signal, defaults to High (1)
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the polarity of the reset signal, defaults to High (1)
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time_init1:
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time_init1:
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the time to wait after Vcc > 4.5 V
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the time to wait after Vcc > 4.5 V
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time_init2:
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time_init2:
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the time to wait after first "contact"
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the time to wait after first "contact"
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time_init3:
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time_init3:
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the time to wait after the second contact
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the time to wait after the second contact
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time_tas:
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time_tas:
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the RW and RS signal setup time with respect to the positive
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the RW and RS signal setup time with respect to the positive
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edge of the E pulse
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edge of the E pulse
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time_cycle_e:
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time_cycle_e:
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the complete cycle time
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the complete cycle time
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time_pweh:
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time_pweh:
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the E pulse width high time
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the E pulse width high time
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time_no_bf:
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time_no_bf:
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time to wait before command completion if no Busy Flag reading is done,
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time to wait before command completion if no Busy Flag reading is done,
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some designs connect RW to logic 0, so reading from the LCD is not
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some designs connect RW to logic 0, so reading from the LCD is not
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possible, saves a pin.
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possible, saves a pin.
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cursor_on:
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cursor_on:
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true to set the cursor on at the display, false for no cursor
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true to set the cursor on at the display, false for no cursor
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blink_on:
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blink_on:
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true to let the cursor blink, false for no blink (just a underscore)
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true to let the cursor blink, false for no blink (just a underscore)
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use_bf: true if Busy Flag reading is to be used, false for no BF reading
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use_bf: true if Busy Flag reading is to be used, false for no BF reading
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Note: it's not possible to write command codes to the display.
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Note: it's not possible to write command codes to the display.
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A note about timing:
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A note about timing:
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Some of the timing parameters are very small, e.g. the RW and RS setup time with
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Some of the timing parameters are very small, e.g. the RW and RS setup time with
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respect to rising edge of E. If the clock frequency is too low, the delay calculated
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respect to rising edge of E. If the clock frequency is too low, the delay calculated
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will be zero, which result in at least a delay with the period time of the clock.
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will be zero, which result in at least a delay with the period time of the clock.
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A note about implementing:
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A note about implementing:
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If the driver doesn't work or you get clobbered strings, please use non-BF
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If the driver doesn't work or you get clobbered strings, please use non-BF
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reading at first. Next, increase the Cycle E time and PWeh time.
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reading at first. Next, increase the Cycle E time and PWeh time.
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