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-- High load test project. ***** TOP level file *****
-- High load test project. ***** TOP level file *****
-- Alexey Fedorov, 2014
-- Alexey Fedorov, 2014
-- email: FPGA@nerudo.com
-- email: FPGA@nerudo.com
--
--
-- It is intended for checking device 
-- It is intended for checking device 
-- for high consumption power.
-- for high consumption power.
-- Number of parameter gives possibility
-- Number of parameter gives possibility
-- to change number of used LC/DFF, DSP, RAM and I/O.
-- to change number of used LC/DFF, DSP, RAM and I/O.
--
--
-- It can operate at 200 MHz in Cyclone 5E FPGA
-- It can operate at 200 MHz in Cyclone 5E FPGA
--
--
--      1 LC core is about 1500 LUT4/FF (with default parameters)
--      1 LC core is about 1500 LUT4/FF (with default parameters)
--  1 DSP core is 7 DSP 18*18.
--  1 DSP core is 7 DSP 18*18.
--  Each LC core also demands 4*N RAM block (32 bits width)
--  Each LC core also demands 4*N RAM block (32 bits width)
 
 
--To maximize power consumption:
--To maximize power consumption:
--1) Find parameters for maximum FPGA resource usage
--1) Find parameters for maximum FPGA resource usage
--2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
--2) Fed maximum frequency clock to CLK input (directly or via PLL instantiated in top level)
--3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
--3) Fed random data to inputs (lower ADC bits or data from PRBS generator)
--4) Connect maximal count of outputs. Be careful: They are switching simultaneously.
--4) Connect maximal count of outputs. Be careful: They are switching simultaneously.
--
--
-- **** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****
-- **** USE HIGH LOAD PROJECT AT YOUR OWN RISK ****
--
--
 
 
 
 
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std.all;
 
 
 
 
entity high_load is
entity high_load is
        generic (
        generic (
                NUM_IN  : positive := 3*14;     -- Input pins
                NUM_IN  : positive := 3*14;     -- Input pins
                NUM_OUT : positive := 1;                -- Output pins
                NUM_OUT : positive := 1;                -- Output pins
                NUM_LC : positive := 16;                -- Number of LC cores
                NUM_LC : positive := 16;                -- Number of LC cores
                NUM_DSP : positive := 9;                -- Number of DSP cores
                NUM_DSP : positive := 9;                -- Number of DSP cores
                RAM_DEPTH_LOG2 : integer range 4 to 30 := 10    -- RAM depth
                RAM_DEPTH_LOG2 : integer range 4 to 30 := 10    -- RAM depth
                );
                );
        port
        port
        (
        (
                -- Input ports
                -- Input ports
                clk     : in  std_logic;
                clk     : in  std_logic;
                inputs: in std_logic_vector(NUM_IN-1 downto 0);
                inputs: in std_logic_vector(NUM_IN-1 downto 0);
 
 
                -- Output ports
                -- Output ports
                dataout: out std_logic_vector(NUM_OUT-1 downto 0)
                dataout: out std_logic_vector(NUM_OUT-1 downto 0)
        );
        );
end high_load;
end high_load;
 
 
 
 
 
 
architecture rtl of high_load is
architecture rtl of high_load is
 
 
--component aes_test_wrap is
--component aes_test_wrap is
--port(
--port(
--              clk     : in  std_logic;
--              clk     : in  std_logic;
--              datain: in std_logic_vector(127 downto 0);
--              datain: in std_logic_vector(127 downto 0);
--              key             : in std_logic_vector(127 downto 0);
--              key             : in std_logic_vector(127 downto 0);
--              dataout: out std_logic_vector(127 downto 0)
--              dataout: out std_logic_vector(127 downto 0)
--      );
--      );
--end component;
--end component;
 
 
component lc_use is
component lc_use is
        generic (
        generic (
                DATA_WIDTH : positive := 128;
                DATA_WIDTH : positive := 128;
                ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
                ARITH_SIZE : positive := 16; -- Should be divider of DATA_WIDTH
                NUM_ROWS: positive := 6 -- Input pins
                NUM_ROWS: positive := 6;        -- Input pins
 
        ADD_PIPL_FF : boolean := false
                );
                );
        port
        port
        (
        (
                clk     : in  std_logic;
                clk     : in  std_logic;
                inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
                inputs: in std_logic_vector(DATA_WIDTH-1 downto 0);
                dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
                dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
        );
end component;
end component;
 
 
component dsp_use is
component dsp_use is
        generic (
        generic (
                DATA_WIDTH  : positive := 16
                DATA_WIDTH  : positive := 16
                );
                );
        port
        port
        (
        (
                clk     : in  std_logic;
                clk     : in  std_logic;
                datain: in std_logic_vector(DATA_WIDTH-1 downto 0);
                datain: in std_logic_vector(DATA_WIDTH-1 downto 0);
                dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
                dataout: out std_logic_vector(DATA_WIDTH-1 downto 0)
        );
        );
end component;
end component;
 
 
component ram_buf IS
component ram_buf IS
        generic (
        generic (
                DATA_WIDTH: positive := 12;
                DATA_WIDTH: positive := 12;
                DEPTH_LOG2: positive := 10
                DEPTH_LOG2: positive := 10
                );
                );
  port(
  port(
    clk    : in  std_logic;         -- input data clock
    clk    : in  std_logic;         -- input data clock
--    ena    : in  std_logic;         -- input data enable
--    ena    : in  std_logic;         -- input data enable
    din    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    din    : in  std_logic_vector(DATA_WIDTH-1 downto 0);
    delay  : in  std_logic_vector(DEPTH_LOG2-1 downto 0);
    delay  : in  std_logic_vector(DEPTH_LOG2-1 downto 0);
    dout   : out std_logic_vector(DATA_WIDTH-1 downto 0)
    dout   : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
    );
END component;
END component;
 
 
constant DSP_WIDTH : integer := 15;     -- Data width of DSP multipliers
constant DSP_WIDTH : integer := 15;     -- Data width of DSP multipliers
 
 
constant LC_W : integer := 128*NUM_LC;
constant LC_W : integer := 128*NUM_LC;
constant DSP_W : integer := DSP_WIDTH*NUM_DSP;
constant DSP_W : integer := DSP_WIDTH*NUM_DSP;
 
 
--constant key : bit_vector(127 downto 0) := X"2BAC93F18E4797830BD476554BBE27A5";
--constant key : bit_vector(127 downto 0) := X"2BAC93F18E4797830BD476554BBE27A5";
 
 
signal lc_in, lc_out, ram_in, ram_out : std_logic_vector(LC_W-1 downto 0);
signal lc_in, lc_out, ram_in, ram_out : std_logic_vector(LC_W-1 downto 0);
signal dsp_in, dsp_out : std_logic_vector(DSP_W-1 downto 0);
signal dsp_in, dsp_out : std_logic_vector(DSP_W-1 downto 0);
 
 
signal xor_result : std_logic;
signal xor_result : std_logic;
 
 
procedure assign_bus(
procedure assign_bus(
        signal inp  : in  std_logic_vector;
        signal inp  : in  std_logic_vector;
        signal outp : out std_logic_vector) is
        signal outp : out std_logic_vector) is
 
 
        constant IN_W : integer := inp'length(1);
        constant IN_W : integer := inp'length(1);
        constant OUT_W: integer := outp'length(1);
        constant OUT_W: integer := outp'length(1);
 
 
        begin
        begin
        for i in 1 to OUT_W/IN_W loop
        for i in 1 to OUT_W/IN_W loop
                if i = 1 then
                if i = 1 then
                        outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp;
                        outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp;
                else
                else
                        outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp xor to_stdlogicvector(to_bitvector(inp) rol (i-1));
                        outp((i-1)*IN_W+IN_W-1 downto (i-1)*IN_W) <= inp xor to_stdlogicvector(to_bitvector(inp) rol (i-1));
                end if;
                end if;
        end loop;
        end loop;
        if OUT_W mod IN_W > 0 then
        if OUT_W mod IN_W > 0 then
                outp(OUT_W-1 downto (OUT_W/IN_W)*IN_W) <= inp(OUT_W mod IN_W - 1 downto 0);
                outp(OUT_W-1 downto (OUT_W/IN_W)*IN_W) <= inp(OUT_W mod IN_W - 1 downto 0);
        end if;
        end if;
end procedure;
end procedure;
 
 
procedure xorbus(
procedure xorbus(
        signal inp  : in  std_logic_vector;
        signal inp  : in  std_logic_vector;
        signal outp : out std_logic
        signal outp : out std_logic
) is
) is
variable tmp : std_logic := '0';
variable tmp : std_logic := '0';
begin
begin
 
 
        for i in inp'range loop
        for i in inp'range loop
                tmp := tmp xor inp(i);
                tmp := tmp xor inp(i);
        end loop;
        end loop;
 
 
        outp <= tmp;
        outp <= tmp;
 
 
end procedure;
end procedure;
 
 
 
 
procedure resultbus(
procedure resultbus(
        signal inp  : in  std_logic_vector;
        signal inp  : in  std_logic_vector;
        signal outp : out std_logic
        signal outp : out std_logic
) is
) is
variable tmp : integer := 0;
variable tmp : integer := 0;
begin
begin
        for i in inp'range loop
        for i in inp'range loop
                if inp(i) = '1' then
                if inp(i) = '1' then
                        tmp := tmp + 1;
                        tmp := tmp + 1;
                end if;
                end if;
        end loop;
        end loop;
 
 
        if tmp >= inp'length(1) then
        if tmp >= inp'length(1) then
                outp <= '1';
                outp <= '1';
        else
        else
                outp <= '0';
                outp <= '0';
        end if;
        end if;
 
 
end procedure;
end procedure;
 
 
 
 
begin
begin
 
 
assert lc_in'length(1) <  dsp_in'length(1) report "Implementing Input => DSP => RAM => LC => Output" severity warning;
assert lc_in'length(1) <  dsp_in'length(1) report "Implementing Input => DSP => RAM => LC => Output" severity warning;
assert lc_in'length(1) >= dsp_in'length(1) report "Implementing Input => LC => RAM => DSP => Output" severity warning;
assert lc_in'length(1) >= dsp_in'length(1) report "Implementing Input => LC => RAM => DSP => Output" severity warning;
 
 
process(clk) --inputs, lc_in, lc_out, ram_in, ram_out, dsp_in, dsp_out, xor_result)
process(clk) --inputs, lc_in, lc_out, ram_in, ram_out, dsp_in, dsp_out, xor_result)
begin
begin
if rising_edge(clk) then
if rising_edge(clk) then
        if(lc_in'length(1) < dsp_in'length(1)) then
        if(lc_in'length(1) < dsp_in'length(1)) then
                assign_bus(inputs, lc_in);      -- Input => LC => RAM => DSP => Output
                assign_bus(inputs, lc_in);      -- Input => LC => RAM => DSP => Output
                assign_bus(lc_out, ram_in);
                assign_bus(lc_out, ram_in);
                assign_bus(ram_out, dsp_in);
                assign_bus(ram_out, dsp_in);
--              resultbus(dsp_out, xor_result);
--              resultbus(dsp_out, xor_result);
                xorbus(dsp_out, xor_result);
                xorbus(dsp_out, xor_result);
                dataout <= (others => xor_result);
                dataout <= (others => xor_result);
        else
        else
                assign_bus(inputs, dsp_in);     -- Input => DSP => RAM => LC => Output
                assign_bus(inputs, dsp_in);     -- Input => DSP => RAM => LC => Output
                assign_bus(dsp_out, ram_in);
                assign_bus(dsp_out, ram_in);
                assign_bus(ram_out, lc_in);
                assign_bus(ram_out, lc_in);
--              resultbus(lc_out, xor_result);
--              resultbus(lc_out, xor_result);
                xorbus(lc_out, xor_result);
                xorbus(lc_out, xor_result);
                dataout <= (others => xor_result);
                dataout <= (others => xor_result);
        end if;
        end if;
end if;
end if;
 
 
end process;
end process;
 
 
 
 
LC_GEN: for i in 0 to NUM_LC-1 generate
LC_GEN: for i in 0 to NUM_LC-1 generate
--      aes_i : aes_test_wrap 
--      aes_i : aes_test_wrap 
--      port map(
--      port map(
--              clk             => clk,
--              clk             => clk,
--              datain => aes_in(128*i+127 downto 128*i),
--              datain => aes_in(128*i+127 downto 128*i),
--              key      => to_stdlogicvector(key rol i),
--              key      => to_stdlogicvector(key rol i),
--              dataout=> aes_out(128*i+127 downto 128*i)
--              dataout=> aes_out(128*i+127 downto 128*i)
--      );
--      );
        lc_i: lc_use
        lc_i: lc_use
        generic map (
        generic map (
                DATA_WIDTH => 128,
                DATA_WIDTH => 128,
                ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
                ARITH_SIZE => 16, -- Should be divider of DATA_WIDTH
                NUM_ROWS         => 6   -- Input pins
                NUM_ROWS         => 6,  -- Input pins
 
                ADD_PIPL_FF => true
                )
                )
        port map
        port map
        (
        (
                clk              => clk,
                clk              => clk,
                inputs => lc_in(128*i+127 downto 128*i),
                inputs => lc_in(128*i+127 downto 128*i),
                dataout=> lc_out(128*i+127 downto 128*i)
                dataout=> lc_out(128*i+127 downto 128*i)
        );
        );
 
 
end generate;
end generate;
 
 
DSP_GEN: for i in 0 to NUM_DSP-1 generate
DSP_GEN: for i in 0 to NUM_DSP-1 generate
 
 
        dsp_i : dsp_use
        dsp_i : dsp_use
        generic map(
        generic map(
                DATA_WIDTH  => DSP_WIDTH)
                DATA_WIDTH  => DSP_WIDTH)
        port map
        port map
        (
        (
                clk                     => clk,
                clk                     => clk,
                datain  => dsp_in(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i),
                datain  => dsp_in(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i),
                dataout => dsp_out(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i)
                dataout => dsp_out(DSP_WIDTH*i+DSP_WIDTH-1 downto DSP_WIDTH*i)
        );
        );
 
 
end generate;
end generate;
 
 
RAM_GEN: for i in 0 to NUM_LC-1 generate
RAM_GEN: for i in 0 to NUM_LC-1 generate
        ram_i: ram_buf
        ram_i: ram_buf
                generic map(
                generic map(
                DATA_WIDTH => 128,
                DATA_WIDTH => 128,
                DEPTH_LOG2 => RAM_DEPTH_LOG2
                DEPTH_LOG2 => RAM_DEPTH_LOG2
                )
                )
                port map(
                port map(
                        clk   => clk,
                        clk   => clk,
                        din   => ram_in(128*i+127 downto 128*i),
                        din   => ram_in(128*i+127 downto 128*i),
                        delay => std_logic_vector(to_unsigned(2**RAM_DEPTH_LOG2-10, RAM_DEPTH_LOG2)),
                        delay => std_logic_vector(to_unsigned(2**RAM_DEPTH_LOG2-10, RAM_DEPTH_LOG2)),
                        dout  => ram_out(128*i+127 downto 128*i)
                        dout  => ram_out(128*i+127 downto 128*i)
    );
    );
end generate;
end generate;
 
 
end rtl;
end rtl;
 
 

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