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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// This file is part of the M32632 project
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// This file is part of the M32632 project
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// http://opencores.org/project,m32632
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// http://opencores.org/project,m32632
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//
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//
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// Filename: ADDR_UNIT.v
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// Filename: ADDR_UNIT.v
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// Version: 2.0
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// Version: 3.0
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// History: 1.1 bug fix of 7 October 2015
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// History: 2.0 of 11 August 2016
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// 1.1 bug fix of 7 October 2015
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// 1.0 first release of 30 Mai 2015
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// 1.0 first release of 30 Mai 2015
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// Date: 14 August 2016
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// Date: 2 December 2018
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//
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//
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// Copyright (C) 2016 Udo Moeller
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// Copyright (C) 2018 Udo Moeller
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//
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//
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// This source file may be used and distributed without
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// This source file may be used and distributed without
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// restriction provided that this copyright statement is not
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// restriction provided that this copyright statement is not
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// removed from the file and that any derivative work contains
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// removed from the file and that any derivative work contains
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// the original copyright notice and the associated disclaimer.
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// the original copyright notice and the associated disclaimer.
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//
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//
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// You should have received a copy of the GNU Lesser General
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// You should have received a copy of the GNU Lesser General
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// Public License along with this source; if not, download it
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// Public License along with this source; if not, download it
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// from http://www.opencores.org/lgpl.shtml
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// from http://www.opencores.org/lgpl.shtml
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//
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//
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// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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//
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//
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// Modules contained in this file:
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// Modules contained in this file:
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// ADDR_UNIT generates data access addresses and controls data cache operation
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// ADDR_UNIT generates data access addresses and controls data cache operation
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//
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//
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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module ADDR_UNIT ( BCLK, BRESET, READ, WRITE, LDEA, NEWACC, CLRMSW, POST, DISP_OK, FULLACC, SRC2SEL, INDEX, ASIZE, SRC1, SRC2, BWD,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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DISP, PC_ARCHI, PC_ICACHE, IO_READY, ACC_STAT, MMU_UPDATE, IC_TEX, ABO_STAT, ADIVAR, RWVAL_1, OP_RMW, PHASE_17,
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, REG_OUT, BITSEL,
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NO_TRAP, FPU_TRAP, READ_OUT, WRITE_OUT, ZTEST, RMW, VADR, ADDR, SIZE, PACKET, ACC_DONE, ABORT, CTRL_QW, BITSEL,
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QWATWO );
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QWATWO );
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input BCLK,BRESET;
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input BCLK,BRESET;
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input READ,WRITE,LDEA;
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input READ,WRITE,LDEA;
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input NEWACC;
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input NEWACC;
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output [31:0] ADDR;
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output [31:0] ADDR;
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output [1:0] SIZE;
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output [1:0] SIZE;
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output [3:0] PACKET;
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output [3:0] PACKET;
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output ACC_DONE;
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output ACC_DONE;
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output ABORT;
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output ABORT;
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output REG_OUT;
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output [1:0] CTRL_QW;
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output [2:0] BITSEL;
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output [2:0] BITSEL;
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output reg QWATWO;
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output reg QWATWO;
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reg [31:0] VADR;
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reg [31:0] VADR;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg READ_OUT,write_reg,ZTEST,RMW;
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reg ABORT;
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reg ABORT;
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reg [1:0] tex_feld;
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reg [1:0] tex_feld;
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reg [2:0] u_ddt;
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reg [2:0] u_ddt;
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reg pg_op;
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reg pg_op;
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reg do_wr;
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reg do_wr;
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reg irdy_flag;
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wire acc_ok,acc_err,io_acc;
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wire acc_ok,acc_err,io_acc;
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wire acc_pass;
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wire acc_pass;
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wire ca_hit;
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wire ca_hit;
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wire [31:0] reg_adder;
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wire [31:0] reg_adder;
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default : sign_ext_src1 = SRC1;
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default : sign_ext_src1 = SRC1;
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endcase
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endcase
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always @(index_sel or sign_ext_src1 or SRC1)
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always @(index_sel or sign_ext_src1 or SRC1)
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casex (index_sel)
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casex (index_sel)
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4'b1_0xx : index_val = sign_ext_src1; // für CASE
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4'b1_0xx : index_val = sign_ext_src1; // f�r CASE
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b1_1xx : index_val = {{ 3{sign_ext_src1[31]}},sign_ext_src1[31:3]}; // for Bit Opcodes
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4'b0_100 : index_val = SRC1;
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4'b0_100 : index_val = SRC1;
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_101 : index_val = {SRC1[30:0],1'b0};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_110 : index_val = {SRC1[29:0],2'b00};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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4'b0_111 : index_val = {SRC1[28:0],3'b000};
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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assign ACC_DONE = acc_run ? (acc_step & ~no_done) : ea_ok;
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// Bugfix of 7.October 2015
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// Bugfix of 7.October 2015
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always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
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always @(posedge BCLK) QWATWO <= acc_run & acc_ok & qwa_flag & ~io_rdy & ca_hit & ~PACKET[3] & (SIZE == 2'b11) & READ_OUT & ~no_done;
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & (io_rdy | ~ca_hit) & acc_ok) | reg_out_i);
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always @(posedge BCLK) reg_out_i <= ~acc_step & BRESET & ((qwa_flag & ~io_rdy & ~ca_hit & acc_ok) | reg_out_i);
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always @(posedge BCLK) io_rdy <= IO_READY & (WRITE_OUT | READ_OUT);
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always @(posedge BCLK) irdy_flag <= (READ_OUT & io_acc) | (irdy_flag & ~IO_READY); // new 25.6.2018
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always @(posedge BCLK) io_rdy <= IO_READY & irdy_flag;
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always @(posedge BCLK) next_reg <= (acc_step & ~qwa_flag) & (SIZE == 2'b11);
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always @(posedge BCLK) next_reg <= acc_step & (qwa_flag ? io_rdy : 1'b1) & (SIZE == 2'b11);
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assign REG_OUT = reg_out_i | next_reg;
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assign CTRL_QW = {qwa_flag,(reg_out_i | next_reg)};
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endmodule
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endmodule
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