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https://opencores.org/ocsvn/next186_soc_pc/next186_soc_pc/trunk
[/] [next186_soc_pc/] [trunk/] [HW/] [ddr_186.ucf] - Diff between revs 2 and 5
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Rev 5 |
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Line 113... |
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NET "AUD_L" LOC = "Y10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
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NET "AUD_L" LOC = "Y10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
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NET "AUD_R" LOC = "V10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
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NET "AUD_R" LOC = "V10" |IOSTANDARD = LVCMOS33 |DRIVE = 2 |SLEW = SLOW ;
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#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
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#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
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NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
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NET "CLK_50MHZ" TNM_NET = CLK_50MHZ;
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TIMESPEC TS_CLK_50MHZ = PERIOD "CLK_50MHZ" 54 ns HIGH 50%;
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TIMESPEC TS_CLK_50MHZ = PERIOD "CLK_50MHZ" 55 ns HIGH 50%;
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#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
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#Created by Constraints Editor (xc3s700an-fgg484-4) - 2013/05/17
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NET "sys_clk_in" TNM_NET = sys_clk_in;
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NET "sys_clk_in" TNM_NET = sys_clk_in;
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TIMESPEC TS_sys_clk_in = PERIOD "sys_clk_in" 8 ns HIGH 50%;
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TIMESPEC TS_sys_clk_in = PERIOD "sys_clk_in" 9 ns HIGH 50%;
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TIMESPEC TS_sys_clk_in = PERIOD "sys_clk_in" 9 ns HIGH 50%;
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TIMESPEC TS_sys_clk_in = PERIOD "sys_clk_in" 9 ns HIGH 50%;
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