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[/] [opb_usblite/] [trunk/] [pcores/] [opb_usblite_v1_00_a/] [hdl/] [vhdl/] [opb_usblite_core.vhd] - Diff between revs 2 and 5

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Rev 2 Rev 5
Line 185... Line 185... 
  constant RX_FIFO_ADR    : std_logic_vector(0 to 1) := "00";
 
  constant RX_FIFO_ADR    : std_logic_vector(0 to 1) := "00";
 
  constant TX_FIFO_ADR    : std_logic_vector(0 to 1) := "01";
 
  constant TX_FIFO_ADR    : std_logic_vector(0 to 1) := "01";
 
  constant STATUS_REG_ADR : std_logic_vector(0 to 1) := "10";
 
  constant STATUS_REG_ADR : std_logic_vector(0 to 1) := "10";
 
  constant CTRL_REG_ADR   : std_logic_vector(0 to 1) := "11";
 
  constant CTRL_REG_ADR   : std_logic_vector(0 to 1) := "11";
 
 
 
 
 
 
 
  --  ADDRESS MAP
 
 
 
  --  ===========
 
 
 
  --  RX FIFO      base + $0
 
 
 
  --  TX FIFO      base + $4
 
 
 
  --  CONTROL REG  base + $8
 
 
 
  --  STATUS REG   base + $C
 
 
 
 
 
 
 
 
 
  -- Read Only
 
  -- Read Only
 
  signal status_Reg : std_logic_vector(7 downto 0);
 
  signal status_Reg : std_logic_vector(7 downto 0);
 
  -- bit 0 rx_Data_Present
 
  -- bit 0 rx_Data_Present
 
  -- bit 1 rx_Buffer_Full
 
  -- bit 1 rx_Buffer_Full
 
  -- bit 2 tx_Buffer_Empty
 
  -- bit 2 tx_Buffer_Empty
 
  -- bit 3 tx_Buffer_Full
 
  -- bit 3 tx_Buffer_Full
 
  -- bit 4 interrupt flag
 
  -- bit 4 interrupt flag
 
 
 
  -- bit 5 not used
 
 
 
  -- bit 6 online flag
 
 
 
  -- bit 7 suspend flag  
 
 
 
 
  -- Write Only
 
  -- Write Only
 
  -- bit 0   Reset_TX_FIFO
 
  -- bit 0   Reset_TX_FIFO -- not used
 
  -- bit 1   Reset_RX_FIFO
 
  -- bit 1   Reset_RX_FIFO -- not used
 
  -- bit 2-3 Dont'Care
 
  -- bit 2-3 Dont'Care
 
  -- bit 4   enable_rxinterrupts
 
  -- bit 4   enable_rxinterrupts
 
  -- bit 5   Dont'Care
 
  -- bit 5   Dont'Care
 
  -- bit 6   enable_txinterrupts
 
  -- bit 6   enable_txinterrupts
 
  -- bit 7   tx_enable
 
  -- bit 7   tx_enable -- not used
 
 
 
 
 
  signal enable_txinterrupts : std_logic;
 
  signal enable_txinterrupts : std_logic;
 
  signal enable_rxinterrupts : std_logic;
 
  signal enable_rxinterrupts : std_logic;
 
 
 
 
 
  signal read_RX_FIFO      : std_logic;
 
  signal read_RX_FIFO      : std_logic;
Line 358... Line 369... 
  status_Reg(3) <= tx_BUFFER_FULL;
 
  status_Reg(3) <= tx_BUFFER_FULL;
 
  status_Reg(4) <= Interrupt_r;
 
  status_Reg(4) <= Interrupt_r;
 
  status_Reg(5) <= '0';
 
  status_Reg(5) <= '0';
 
  status_Reg(6) <= online;
 
  status_Reg(6) <= online;
 
  status_Reg(7) <= suspend;
 
  status_Reg(7) <= suspend;
 
--  status_Reg(6) <= '0';
 
 
 
--  status_Reg(7) <= '0';
 
 
 
 
 
 
 
 
 
 
 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------
 
  -- Control / Status Register Handling 
  -- Control / Status Register Handling 
  -----------------------------------------------------------------------------
 
  -----------------------------------------------------------------------------

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