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//-------------------------------------------------------------------------------------
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//
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// Author: John Clayton
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// Date : April 30, 2001
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// Update: 4/30/01 copied this file from lcd_2.v (pared down).
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// Update: 5/24/01 changed the first module from "ps2_keyboard_receiver"
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// to "ps2_keyboard_interface"
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// Update: 5/29/01 Added input synchronizing flip-flops. Changed state
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// encoding (m1) for good operation after part config.
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// Update: 5/31/01 Added low drive strength and slow transitions to ps2_clk
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// and ps2_data in the constraints file. Added the signal
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// "tx_shifting_done" as distinguished from "rx_shifting_done."
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// Debugged the transmitter portion in the lab.
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// Update: 6/01/01 Added horizontal tab to the ascii output.
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// Update: 6/01/01 Added parameter TRAP_SHIFT_KEYS.
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// Update: 6/05/01 Debugged the "debounce" timer functionality.
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// Used 60usec timer as a "watchdog" timeout during
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// receive from the keyboard. This means that a keyboard
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// can now be "hot plugged" into the interface, without
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// messing up the bit_count, since the bit_count is reset
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// to zero during periods of inactivity anyway. This was
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// difficult to debug. I ended up using the logic analyzer,
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// and had to scratch my head quite a bit.
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// Update: 6/06/01 Removed extra comments before the input synchronizing
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// flip-flops. Used the correct parameter to size the
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// 5usec_timer_count. Changed the name of this file from
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// ps2.v to ps2_keyboard.v
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// Update: 6/06/01 Removed "&& q[7:0]" in output_strobe logic. Removed extra
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// commented out "else" condition in the shift register and
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// bit counter.
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// Update: 6/07/01 Changed default values for 60usec timer parameters so that
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// they correspond to 60usec for a 49.152MHz clock.
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//
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//
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//
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//
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//
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// Description
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//-------------------------------------------------------------------------------------
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// This is a state-machine driven serial-to-parallel and parallel-to-serial
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// interface to the ps2 style keyboard interface. The details of the operation
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// of the keyboard interface were obtained from the following website:
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//
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// http://www.beyondlogic.org/keyboard/keybrd.htm
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//
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// Some aspects of the keyboard interface are not implemented (e.g, parity
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// checking for the receive side, and recognition of the various commands
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// which the keyboard sends out, such as "power on selt test passed," "Error"
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// and "Resend.") However, if the user wishes to recognize these reply
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// messages, the scan code output can always be used to extend functionality
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// as desired.
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//
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// Note that the "Extended" (0xE0) and "Released" (0xF0) codes are recognized.
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// The rx interface provides separate indicator flags for these two conditions
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// with every valid character scan code which it provides. The shift keys are
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// also trapped by the interface, in order to provide correct uppercase ASCII
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// characters at the ascii output, although the scan codes for the shift keys
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// are still provided at the scan code output. So, the left/right ALT keys
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// can be differentiated by the presence of the rx_entended signal, while the
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// left/right shift keys are differentiable by the different scan codes
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// received.
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//
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// The interface to the ps2 keyboard uses ps2_clk clock rates of
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// 30-40 kHz, dependent upon the keyboard itself. The rate at which the state
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// machine runs should be at least twice the rate of the ps2_clk, so that the
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// states can accurately follow the clock signal itself. Four times
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// oversampling is better. Say 200kHz at least. The upper limit for clocking
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// the state machine will undoubtedly be determined by delays in the logic
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// which decodes the scan codes into ASCII equivalents. The maximum speed
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// will be most likely many megahertz, depending upon target technology.
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// In order to run the state machine extremely fast, synchronizing flip-flops
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// have been added to the ps2_clk and ps2_data inputs of the state machine.
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// This avoids poor performance related to slow transitions of the inputs.
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//
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// Because this is a bi-directional interface, while reading from the keyboard
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// the ps2_clk and ps2_data lines are used as inputs. While writing to the
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// keyboard, however (which may be done at any time. If writing interrupts a
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// read from the keyboard, the keyboard will buffer up its data, and send
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// it later) both the ps2_clk and ps2_data lines are occasionally pulled low,
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// and pullup resistors are used to bring the lines high again, by setting
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// the drivers to high impedance state.
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//
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// The tx interface, for writing to the keyboard, does not provide any special
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// pre-processing. It simply transmits the 8-bit command value to the
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// keyboard.
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//
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// Pullups MUST BE USED on the ps2_clk and ps2_data lines for this design,
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// whether they be internal to an FPGA I/O pad, or externally placed.
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// If internal pullups are used, they may be fairly weak, causing bounces
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// due to crosstalk, etc. There is a "debounce timer" implemented in order
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// to eliminate erroneous state transitions which would occur based on bounce.
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//
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// Parameters are provided in order to configure and appropriately size the
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// counter of a 60 microsecond timer used in the transmitter, depending on
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// the clock frequency used. The 60 microsecond period is guaranteed to be
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// more than one period of the ps2_clk_s signal.
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//
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// Also, a smaller 5 microsecond timer has been included for "debounce".
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// This is used because, with internal pullups on the ps2_clk and ps2_data
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// lines, there is some bouncing around which occurs
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//
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// A parameter TRAP_SHIFT_KEYS allows the user to eliminate shift keypresses
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// from producing scan codes (along with their "undefined" ASCII equivalents)
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// at the output of the interface. If TRAP_SHIFT_KEYS is non-zero, the shift
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// key status will only be reported by rx_shift_key_on. No ascii or scan
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// codes will be reported for the shift keys. This is useful for those who
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// wish to use the ASCII data stream, and who don't want to have to "filter
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// out" the shift key codes.
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//
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//-------------------------------------------------------------------------------------
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`resetall
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`timescale 1ns/100ps
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`define TOTAL_BITS 11
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`define EXTEND_CODE 16'hE0
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`define RELEASE_CODE 16'hF0
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`define LEFT_SHIFT 16'h12
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`define RIGHT_SHIFT 16'h59
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module ps2_keyboard_interface (
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clk,
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reset,
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ps2_clk,
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ps2_data,
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rx_extended,
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rx_released,
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rx_shift_key_on,
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rx_scan_code,
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rx_ascii,
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rx_data_ready, // rx_read_o
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rx_read, // rx_read_ack_i
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tx_data,
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tx_write,
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tx_write_ack_o,
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tx_error_no_keyboard_ack
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);
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// Parameters
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// The timer value can be up to (2^bits) inclusive.
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parameter TIMER_60USEC_VALUE_PP = 2950; // Number of sys_clks for 60usec.
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parameter TIMER_60USEC_BITS_PP = 12; // Number of bits needed for timer
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parameter TIMER_5USEC_VALUE_PP = 186; // Number of sys_clks for debounce
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parameter TIMER_5USEC_BITS_PP = 8; // Number of bits needed for timer
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parameter TRAP_SHIFT_KEYS_PP = 0; // Default: No shift key trap.
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// State encodings, provided as parameters
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// for flexibility to the one instantiating the module.
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// In general, the default values need not be changed.
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// State "m1_rx_clk_l" has been chosen on purpose. Since the input
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// synchronizing flip-flops initially contain zero, it takes one clk
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// for them to update to reflect the actual (idle = high) status of
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// the I/O lines from the keyboard. Therefore, choosing 0 for m1_rx_clk_l
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// allows the state machine to transition to m1_rx_clk_h when the true
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// values of the input signals become present at the outputs of the
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// synchronizing flip-flops. This initial transition is harmless, and it
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// eliminates the need for a "reset" pulse before the interface can operate.
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parameter m1_rx_clk_h = 1;
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parameter m1_rx_clk_l = 0;
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parameter m1_rx_falling_edge_marker = 13;
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parameter m1_rx_rising_edge_marker = 14;
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parameter m1_tx_force_clk_l = 3;
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parameter m1_tx_first_wait_clk_h = 10;
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parameter m1_tx_first_wait_clk_l = 11;
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parameter m1_tx_reset_timer = 12;
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parameter m1_tx_wait_clk_h = 2;
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parameter m1_tx_clk_h = 4;
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parameter m1_tx_clk_l = 5;
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parameter m1_tx_wait_keyboard_ack = 6;
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parameter m1_tx_done_recovery = 7;
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parameter m1_tx_error_no_keyboard_ack = 8;
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parameter m1_tx_rising_edge_marker = 9;
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parameter m2_rx_data_ready = 1;
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parameter m2_rx_data_ready_ack = 0;
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// I/O declarations
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input clk;
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input reset;
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inout ps2_clk;
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inout ps2_data;
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output rx_extended;
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output rx_released;
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output rx_shift_key_on;
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output [7:0] rx_scan_code;
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output [7:0] rx_ascii;
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output rx_data_ready;
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input rx_read;
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input [7:0] tx_data;
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input tx_write;
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output tx_write_ack_o;
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output tx_error_no_keyboard_ack;
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reg rx_extended;
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reg rx_released;
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reg [7:0] rx_scan_code;
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reg [7:0] rx_ascii;
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reg rx_data_ready;
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reg tx_error_no_keyboard_ack;
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// Internal signal declarations
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wire timer_60usec_done;
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wire timer_5usec_done;
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wire extended;
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wire released;
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wire shift_key_on;
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// NOTE: These two signals used to be one. They
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// were split into two signals because of
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// shift key trapping. With shift key
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// trapping, no event is generated externally,
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// but the "hold" data must still be cleared
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// anyway regardless, in preparation for the
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// next scan codes.
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wire rx_output_event; // Used only to clear: hold_released, hold_extended
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wire rx_output_strobe; // Used to produce the actual output.
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wire tx_parity_bit;
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wire rx_shifting_done;
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wire tx_shifting_done;
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wire [11:0] shift_key_plus_code;
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reg [`TOTAL_BITS-1:0] q;
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reg [3:0] m1_state;
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reg [3:0] m1_next_state;
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reg m2_state;
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reg m2_next_state;
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reg [3:0] bit_count;
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reg enable_timer_60usec;
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reg enable_timer_5usec;
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reg [TIMER_60USEC_BITS_PP-1:0] timer_60usec_count;
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reg [TIMER_5USEC_BITS_PP-1:0] timer_5usec_count;
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reg [7:0] ascii; // "REG" type only because a case statement is used.
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reg left_shift_key;
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reg right_shift_key;
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reg hold_extended; // Holds prior value, cleared at rx_output_strobe
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reg hold_released; // Holds prior value, cleared at rx_output_strobe
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reg ps2_clk_s; // Synchronous version of this input
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reg ps2_data_s; // Synchronous version of this input
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reg ps2_clk_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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reg ps2_data_hi_z; // Without keyboard, high Z equals 1 due to pullups.
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//--------------------------------------------------------------------------
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// Module code
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assign ps2_clk = ps2_clk_hi_z?1'bZ:1'b0;
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assign ps2_data = ps2_data_hi_z?1'bZ:1'b0;
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// Input "synchronizing" logic -- synchronizes the inputs to the state
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// machine clock, thus avoiding errors related to
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// spurious state machine transitions.
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always @(posedge clk)
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begin
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ps2_clk_s <= ps2_clk;
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ps2_data_s <= ps2_data;
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end
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// State register
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always @(posedge clk)
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begin : m1_state_register
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if (reset) m1_state <= m1_rx_clk_h;
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else m1_state <= m1_next_state;
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end
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// State transition logic
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always @(m1_state
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or q
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or tx_shifting_done
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or tx_write
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or ps2_clk_s
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or ps2_data_s
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or timer_60usec_done
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or timer_5usec_done
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)
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begin : m1_state_logic
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// Output signals default to this value, unless changed in a state condition.
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ps2_clk_hi_z <= 1;
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ps2_data_hi_z <= 1;
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tx_error_no_keyboard_ack <= 0;
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enable_timer_60usec <= 0;
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enable_timer_5usec <= 0;
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case (m1_state)
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m1_rx_clk_h :
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begin
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enable_timer_60usec <= 1;
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if (tx_write) m1_next_state <= m1_tx_reset_timer;
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else if (~ps2_clk_s) m1_next_state <= m1_rx_falling_edge_marker;
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else m1_next_state <= m1_rx_clk_h;
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end
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m1_rx_falling_edge_marker :
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begin
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_l;
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end
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m1_rx_rising_edge_marker :
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begin
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enable_timer_60usec <= 0;
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m1_next_state <= m1_rx_clk_h;
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end
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m1_rx_clk_l :
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begin
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enable_timer_60usec <= 1;
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if (tx_write) m1_next_state <= m1_tx_reset_timer;
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else if (ps2_clk_s) m1_next_state <= m1_rx_rising_edge_marker;
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else m1_next_state <= m1_rx_clk_l;
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end
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m1_tx_reset_timer:
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begin
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enable_timer_60usec <= 0;
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m1_next_state <= m1_tx_force_clk_l;
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end
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m1_tx_force_clk_l :
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begin
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enable_timer_60usec <= 1;
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ps2_clk_hi_z <= 0; // Force the ps2_clk line low.
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if (timer_60usec_done) m1_next_state <= m1_tx_first_wait_clk_h;
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else m1_next_state <= m1_tx_force_clk_l;
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end
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m1_tx_first_wait_clk_h :
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begin
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enable_timer_5usec <= 1;
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ps2_data_hi_z <= 0; // Start bit.
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if (~ps2_clk_s && timer_5usec_done)
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m1_next_state <= m1_tx_clk_l;
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else
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m1_next_state <= m1_tx_first_wait_clk_h;
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end
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// This state must be included because the device might possibly
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// delay for up to 10 milliseconds before beginning its clock pulses.
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// During that waiting time, we cannot drive the data (q[0]) because it
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// is possibly 1, which would cause the keyboard to abort its receive
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// and the expected clocks would then never be generated.
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m1_tx_first_wait_clk_l :
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begin
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ps2_data_hi_z <= 0;
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if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
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else m1_next_state <= m1_tx_first_wait_clk_l;
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end
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m1_tx_wait_clk_h :
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begin
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enable_timer_5usec <= 1;
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ps2_data_hi_z <= q[0];
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if (ps2_clk_s && timer_5usec_done)
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m1_next_state <= m1_tx_rising_edge_marker;
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else
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m1_next_state <= m1_tx_wait_clk_h;
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end
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m1_tx_rising_edge_marker :
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begin
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ps2_data_hi_z <= q[0];
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m1_next_state <= m1_tx_clk_h;
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end
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m1_tx_clk_h :
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begin
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ps2_data_hi_z <= q[0];
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if (tx_shifting_done) m1_next_state <= m1_tx_wait_keyboard_ack;
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else if (~ps2_clk_s) m1_next_state <= m1_tx_clk_l;
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else m1_next_state <= m1_tx_clk_h;
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end
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m1_tx_clk_l :
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begin
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ps2_data_hi_z <= q[0];
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if (ps2_clk_s) m1_next_state <= m1_tx_wait_clk_h;
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else m1_next_state <= m1_tx_clk_l;
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end
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m1_tx_wait_keyboard_ack :
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begin
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if (~ps2_clk_s && ps2_data_s)
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m1_next_state <= m1_tx_error_no_keyboard_ack;
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else if (~ps2_clk_s && ~ps2_data_s)
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m1_next_state <= m1_tx_done_recovery;
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else m1_next_state <= m1_tx_wait_keyboard_ack;
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end
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m1_tx_done_recovery :
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begin
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if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
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else m1_next_state <= m1_tx_done_recovery;
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end
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m1_tx_error_no_keyboard_ack :
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begin
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tx_error_no_keyboard_ack <= 1;
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if (ps2_clk_s && ps2_data_s) m1_next_state <= m1_rx_clk_h;
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else m1_next_state <= m1_tx_error_no_keyboard_ack;
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end
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default : m1_next_state <= m1_rx_clk_h;
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endcase
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end
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// State register
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always @(posedge clk)
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begin : m2_state_register
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if (reset) m2_state <= m2_rx_data_ready_ack;
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else m2_state <= m2_next_state;
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end
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// State transition logic
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always @(m2_state or rx_output_strobe or rx_read)
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begin : m2_state_logic
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case (m2_state)
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m2_rx_data_ready_ack:
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begin
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rx_data_ready <= 1'b0;
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if (rx_output_strobe) m2_next_state <= m2_rx_data_ready;
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else m2_next_state <= m2_rx_data_ready_ack;
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end
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m2_rx_data_ready:
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begin
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rx_data_ready <= 1'b1;
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if (rx_read) m2_next_state <= m2_rx_data_ready_ack;
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else m2_next_state <= m2_rx_data_ready;
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end
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default : m2_next_state <= m2_rx_data_ready_ack;
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endcase
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end
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// This is the bit counter
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always @(posedge clk)
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begin
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if ( reset
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|| rx_shifting_done
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|| (m1_state == m1_tx_wait_keyboard_ack) // After tx is done.
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) bit_count <= 0; // normal reset
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else if (timer_60usec_done
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&& (m1_state == m1_rx_clk_h)
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&& (ps2_clk_s)
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) bit_count <= 0; // rx watchdog timer reset
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else if ( (m1_state == m1_rx_falling_edge_marker) // increment for rx
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||(m1_state == m1_tx_rising_edge_marker) // increment for tx
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)
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bit_count <= bit_count + 1;
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end
|
|
// This signal is high for one clock at the end of the timer count.
|
|
assign rx_shifting_done = (bit_count == `TOTAL_BITS);
|
|
assign tx_shifting_done = (bit_count == `TOTAL_BITS-1);
|
|
|
|
// This is the signal which enables loading of the shift register.
|
|
// It also indicates "ack" to the device writing to the transmitter.
|
|
assign tx_write_ack_o = ( (tx_write && (m1_state == m1_rx_clk_h))
|
|
||(tx_write && (m1_state == m1_rx_clk_l))
|
|
);
|
|
|
|
// This is the ODD parity bit for the transmitted word.
|
|
assign tx_parity_bit = ~^tx_data;
|
|
|
|
// This is the shift register
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset) q <= 0;
|
|
else if (tx_write_ack_o) q <= {1'b1,tx_parity_bit,tx_data,1'b0};
|
|
else if ( (m1_state == m1_rx_falling_edge_marker)
|
|
||(m1_state == m1_tx_rising_edge_marker) )
|
|
q <= {ps2_data_s,q[`TOTAL_BITS-1:1]};
|
|
end
|
|
|
|
// This is the 60usec timer counter
|
|
always @(posedge clk)
|
|
begin
|
|
if (~enable_timer_60usec) timer_60usec_count <= 0;
|
|
else if (~timer_60usec_done) timer_60usec_count <= timer_60usec_count + 1;
|
|
end
|
|
assign timer_60usec_done = (timer_60usec_count == (TIMER_60USEC_VALUE_PP - 1));
|
|
|
|
// This is the 5usec timer counter
|
|
always @(posedge clk)
|
|
begin
|
|
if (~enable_timer_5usec) timer_5usec_count <= 0;
|
|
else if (~timer_5usec_done) timer_5usec_count <= timer_5usec_count + 1;
|
|
end
|
|
assign timer_5usec_done = (timer_5usec_count == TIMER_5USEC_VALUE_PP - 1);
|
|
|
|
|
|
// Create the signals which indicate special scan codes received.
|
|
// These are the "unlatched versions."
|
|
assign extended = (q[8:1] == `EXTEND_CODE) && rx_shifting_done;
|
|
assign released = (q[8:1] == `RELEASE_CODE) && rx_shifting_done;
|
|
|
|
// Store the special scan code status bits
|
|
// Not the final output, but an intermediate storage place,
|
|
// until the entire set of output data can be assembled.
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset || rx_output_event)
|
|
begin
|
|
hold_extended <= 0;
|
|
hold_released <= 0;
|
|
end
|
|
else
|
|
begin
|
|
if (rx_shifting_done && extended) hold_extended <= 1;
|
|
if (rx_shifting_done && released) hold_released <= 1;
|
|
end
|
|
end
|
|
|
|
|
|
// These bits contain the status of the two shift keys
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset) left_shift_key <= 0;
|
|
else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && ~hold_released)
|
|
left_shift_key <= 1;
|
|
else if ((q[8:1] == `LEFT_SHIFT) && rx_shifting_done && hold_released)
|
|
left_shift_key <= 0;
|
|
end
|
|
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset) right_shift_key <= 0;
|
|
else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && ~hold_released)
|
|
right_shift_key <= 1;
|
|
else if ((q[8:1] == `RIGHT_SHIFT) && rx_shifting_done && hold_released)
|
|
right_shift_key <= 0;
|
|
end
|
|
|
|
assign rx_shift_key_on = left_shift_key || right_shift_key;
|
|
|
|
// Output the special scan code flags, the scan code and the ascii
|
|
always @(posedge clk)
|
|
begin
|
|
if (reset)
|
|
begin
|
|
rx_extended <= 0;
|
|
rx_released <= 0;
|
|
rx_scan_code <= 0;
|
|
rx_ascii <= 0;
|
|
end
|
|
else if (rx_output_strobe)
|
|
begin
|
|
rx_extended <= hold_extended;
|
|
rx_released <= hold_released;
|
|
rx_scan_code <= q[8:1];
|
|
rx_ascii <= ascii;
|
|
end
|
|
end
|
|
|
|
// Store the final rx output data only when all extend and release codes
|
|
// are received and the next (actual key) scan code is also ready.
|
|
// (the presence of rx_extended or rx_released refers to the
|
|
// the current latest scan code received, not the previously latched flags.)
|
|
assign rx_output_event = (rx_shifting_done
|
|
&& ~extended
|
|
&& ~released
|
|
);
|
|
|
|
assign rx_output_strobe = (rx_shifting_done
|
|
&& ~extended
|
|
&& ~released
|
|
&& ( (TRAP_SHIFT_KEYS_PP == 0)
|
|
|| ( (q[8:1] != `RIGHT_SHIFT)
|
|
&&(q[8:1] != `LEFT_SHIFT)
|
|
)
|
|
)
|
|
);
|
|
|
|
// This part translates the scan code into an ASCII value...
|
|
// Only the ASCII codes which I considered important have been included.
|
|
// if you want more, just add the appropriate case statement lines...
|
|
// (You will need to know the keyboard scan codes you wish to assign.)
|
|
// The entries are listed in ascending order of ASCII value.
|
|
assign shift_key_plus_code = {3'b0,rx_shift_key_on,q[8:1]};
|
|
always @(shift_key_plus_code)
|
|
begin
|
|
casez (shift_key_plus_code)
|
|
12'h?66 : ascii <= 8'h08; // Backspace ("backspace" key)
|
|
12'h?0d : ascii <= 8'h09; // Horizontal Tab
|
|
12'h?5a : ascii <= 8'h0d; // Carriage return ("enter" key)
|
|
12'h?76 : ascii <= 8'h1b; // Escape ("esc" key)
|
|
12'h?29 : ascii <= 8'h20; // Space
|
|
12'h116 : ascii <= 8'h21; // !
|
|
12'h152 : ascii <= 8'h22; // "
|
|
12'h126 : ascii <= 8'h23; // #
|
|
12'h125 : ascii <= 8'h24; // $
|
|
12'h12e : ascii <= 8'h25; // %
|
|
12'h13d : ascii <= 8'h26; // &
|
|
12'h052 : ascii <= 8'h27; // '
|
|
12'h146 : ascii <= 8'h28; // (
|
|
12'h145 : ascii <= 8'h29; // )
|
|
12'h13e : ascii <= 8'h2a; // *
|
|
12'h155 : ascii <= 8'h2b; // +
|
|
12'h041 : ascii <= 8'h2c; // ,
|
|
12'h04e : ascii <= 8'h2d; // -
|
|
12'h049 : ascii <= 8'h2e; // .
|
|
12'h04a : ascii <= 8'h2f; // /
|
|
12'h045 : ascii <= 8'h30; // 0
|
|
12'h016 : ascii <= 8'h31; // 1
|
|
12'h01e : ascii <= 8'h32; // 2
|
|
12'h026 : ascii <= 8'h33; // 3
|
|
12'h025 : ascii <= 8'h34; // 4
|
|
12'h02e : ascii <= 8'h35; // 5
|
|
12'h036 : ascii <= 8'h36; // 6
|
|
12'h03d : ascii <= 8'h37; // 7
|
|
12'h03e : ascii <= 8'h38; // 8
|
|
12'h046 : ascii <= 8'h39; // 9
|
|
12'h14c : ascii <= 8'h3a; // :
|
|
12'h04c : ascii <= 8'h3b; // ;
|
|
12'h141 : ascii <= 8'h3c; // <
|
|
12'h055 : ascii <= 8'h3d; // =
|
|
12'h149 : ascii <= 8'h3e; // >
|
|
12'h14a : ascii <= 8'h3f; // ?
|
|
12'h11e : ascii <= 8'h40; // @
|
|
12'h11c : ascii <= 8'h41; // A
|
|
12'h132 : ascii <= 8'h42; // B
|
|
12'h121 : ascii <= 8'h43; // C
|
|
12'h123 : ascii <= 8'h44; // D
|
|
12'h124 : ascii <= 8'h45; // E
|
|
12'h12b : ascii <= 8'h46; // F
|
|
12'h134 : ascii <= 8'h47; // G
|
|
12'h133 : ascii <= 8'h48; // H
|
|
12'h143 : ascii <= 8'h49; // I
|
|
12'h13b : ascii <= 8'h4a; // J
|
|
12'h142 : ascii <= 8'h4b; // K
|
|
12'h14b : ascii <= 8'h4c; // L
|
|
12'h13a : ascii <= 8'h4d; // M
|
|
12'h131 : ascii <= 8'h4e; // N
|
|
12'h144 : ascii <= 8'h4f; // O
|
|
12'h14d : ascii <= 8'h50; // P
|
|
12'h115 : ascii <= 8'h51; // Q
|
|
12'h12d : ascii <= 8'h52; // R
|
|
12'h11b : ascii <= 8'h53; // S
|
|
12'h12c : ascii <= 8'h54; // T
|
|
12'h13c : ascii <= 8'h55; // U
|
|
12'h12a : ascii <= 8'h56; // V
|
|
12'h11d : ascii <= 8'h57; // W
|
|
12'h122 : ascii <= 8'h58; // X
|
|
12'h135 : ascii <= 8'h59; // Y
|
|
12'h11a : ascii <= 8'h5a; // Z
|
|
12'h054 : ascii <= 8'h5b; // [
|
|
12'h05d : ascii <= 8'h5c; // \
|
|
12'h05b : ascii <= 8'h5d; // ]
|
|
12'h136 : ascii <= 8'h5e; // ^
|
|
12'h14e : ascii <= 8'h5f; // _
|
|
12'h00e : ascii <= 8'h60; // `
|
|
12'h01c : ascii <= 8'h61; // a
|
|
12'h032 : ascii <= 8'h62; // b
|
|
12'h021 : ascii <= 8'h63; // c
|
|
12'h023 : ascii <= 8'h64; // d
|
|
12'h024 : ascii <= 8'h65; // e
|
|
12'h02b : ascii <= 8'h66; // f
|
|
12'h034 : ascii <= 8'h67; // g
|
|
12'h033 : ascii <= 8'h68; // h
|
|
12'h043 : ascii <= 8'h69; // i
|
|
12'h03b : ascii <= 8'h6a; // j
|
|
12'h042 : ascii <= 8'h6b; // k
|
|
12'h04b : ascii <= 8'h6c; // l
|
|
12'h03a : ascii <= 8'h6d; // m
|
|
12'h031 : ascii <= 8'h6e; // n
|
|
12'h044 : ascii <= 8'h6f; // o
|
|
12'h04d : ascii <= 8'h70; // p
|
|
12'h015 : ascii <= 8'h71; // q
|
|
12'h02d : ascii <= 8'h72; // r
|
|
12'h01b : ascii <= 8'h73; // s
|
|
12'h02c : ascii <= 8'h74; // t
|
|
12'h03c : ascii <= 8'h75; // u
|
|
12'h02a : ascii <= 8'h76; // v
|
|
12'h01d : ascii <= 8'h77; // w
|
|
12'h022 : ascii <= 8'h78; // x
|
|
12'h035 : ascii <= 8'h79; // y
|
|
12'h01a : ascii <= 8'h7a; // z
|
|
12'h154 : ascii <= 8'h7b; // {
|
|
12'h15d : ascii <= 8'h7c; // |
|
|
12'h15b : ascii <= 8'h7d; // }
|
|
12'h10e : ascii <= 8'h7e; // ~
|
|
12'h?71 : ascii <= 8'h7f; // (Delete OR DEL on numeric keypad)
|
|
default : ascii <= 8'h2e; // '.' used for unlisted characters.
|
|
endcase
|
|
end
|
|
|
|
|
|
endmodule
|
|
|
|
//`undefine TOTAL_BITS
|
|
//`undefine EXTEND_CODE
|
|
//`undefine RELEASE_CODE
|
|
//`undefine LEFT_SHIFT
|
|
//`undefine RIGHT_SHIFT
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
