`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2007-2017 Robert Finch, Waterloo
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// \\__/ o\ (C) 2007-2017 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// PSG32.v
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// PSG32.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//
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//
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// Registers
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// Registers
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// 00 -------- ffffffff ffffffff ffffffff freq [23:0]
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// 00 -------- ffffffff ffffffff ffffffff freq [23:0]
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// 04 -------- -------- pppppppp pppppppp pulse width
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// 04 -------- -------- pppppppp pppppppp pulse width
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// 08 -------- -------- trsg--fo -vvvvv-- test, ringmod, sync, gate, filter, output, voice type
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// 08 -------- -------- trsg-efo vvvvvv-- test, ringmod, sync, gate, filter, output, voice type
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// 0C aaaaaaaa aaaaaaaa dddddddd dddddddd attack, decay
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// 0C -------- aaaaaaaa aaaaaaaa aaaaaaaa attack
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// 10 -------- ssssssss rrrrrrrr rrrrrrrr sustain, release
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// 10 -------- dddddddd dddddddd dddddddd decay
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// 14 -------- -------- --aaaaaa aaaaaaa- wave table base address
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// 14 -------- -------- -------- ssssssss sustain
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// 18 -------- rrrrrrrr rrrrrrrr rrrrrrrr release
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// 1C -------- -------- --aaaaaa aaaaaaa- wave table base address
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// vvvvv
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// vvvvv
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// wnpst
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// wnpst
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// 18-2C Voice #2
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// 20-3C Voice #2
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// 30-44 Voice #3
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// 40-5C Voice #3
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// 48-5C Voice #4
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// 60-7C Voice #4
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//
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//
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// ...
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// ...
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// B0 -------- -------- -------- vvvvvvvv volume (0-255)
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// B0 -------- -------- -------- ----vvvv volume (0-255)
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// B4 nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn osc3 oscillator 3
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// B4 nnnnnnnn nnnnnnnn nnnnnnnn nnnnnnnn osc3 oscillator 3
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// B8 -------- -------- -------- nnnnnnnn env3 envelope 3
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// B8 -------- -------- -------- nnnnnnnn env3 envelope 3
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// BC -------- -------- -sss-sss -sss-sss env state
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//
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//
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// C0-DC -------- -------- s---kkkk kkkkkkkk filter coefficients
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// C0-DC -------- -------- s---kkkk kkkkkkkk filter coefficients
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// E0-FC -------- -------- -------- -------- reserved for more filter coefficients
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// E0-FC -------- -------- -------- -------- reserved for more filter coefficients
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//
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//
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//=============================================================================
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//=============================================================================
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module PSG32(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,
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module PSG32(rst_i, clk_i, cs_i, cyc_i, stb_i, ack_o, we_i, adr_i, dat_i, dat_o,
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m_adr_o, m_dat_i, o
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m_adr_o, m_dat_i, o
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);
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);
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parameter pClkDivide = 37;
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parameter pClkDivide = 37;
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// WISHBONE SYSCON
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// WISHBONE SYSCON
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input rst_i;
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input rst_i;
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input clk_i; // system clock
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input clk_i; // system clock
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// NON-WISHBONE
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// NON-WISHBONE
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input cs_i; // circuit select
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input cs_i; // circuit select
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// WISHBONE SLAVE
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// WISHBONE SLAVE
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input cyc_i; // cycle valid
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input cyc_i; // cycle valid
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input stb_i; // circuit select
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input stb_i; // circuit select
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output ack_o;
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output ack_o;
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input we_i; // write
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input we_i; // write
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input [7:0] adr_i; // address input
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input [7:0] adr_i; // address input
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input [31:0] dat_i; // data input
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input [31:0] dat_i; // data input
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output [31:0] dat_o; // data output
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output [31:0] dat_o; // data output
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// WISHBONE MASTER
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// WISHBONE MASTER
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output [13:0] m_adr_o; // wave table address
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output [13:0] m_adr_o; // wave table address
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input [11:0] m_dat_i; // wave table data input
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input [11:0] m_dat_i; // wave table data input
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output [17:0] o;
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output [17:0] o;
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// I/O registers
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// I/O registers
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reg [31:0] dat_o;
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reg [31:0] dat_o;
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reg [13:0] m_adr_o;
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reg [13:0] m_adr_o;
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reg [3:0] test; // test (enable note generator)
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reg [3:0] test; // test (enable note generator)
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reg [4:0] vt [3:0]; // voice type
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reg [5:0] vt [3:0]; // voice type
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reg [23:0] freq0, freq1, freq2, freq3; // frequency control
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reg [23:0] freq0, freq1, freq2, freq3; // frequency control
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reg [15:0] pw0, pw1, pw2, pw3; // pulse width control
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reg [15:0] pw0, pw1, pw2, pw3; // pulse width control
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reg [3:0] gate;
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reg [3:0] gate;
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reg [15:0] attack0, attack1, attack2, attack3;
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reg [23:0] attack0, attack1, attack2, attack3;
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reg [15:0] decay0, decay1, decay2, decay3;
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reg [23:0] decay0, decay1, decay2, decay3;
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reg [7:0] sustain0, sustain1, sustain2, sustain3;
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reg [7:0] sustain0, sustain1, sustain2, sustain3;
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reg [15:0] relese0, relese1, relese2, relese3;
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reg [23:0] relese0, relese1, relese2, relese3;
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reg [13:0] wtadr0, wtadr1, wtadr2, wtadr3;
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reg [13:0] wtadr0, wtadr1, wtadr2, wtadr3;
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reg [3:0] sync;
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reg [3:0] sync;
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reg [3:0] ringmod;
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reg [3:0] ringmod;
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reg [3:0] outctrl;
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reg [3:0] outctrl;
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reg [3:0] filt; // 1 = output goes to filter
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reg [3:0] filt; // 1 = output goes to filter
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reg [3:0] eg; // 1 = output goes through envelope generator
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wire [31:0] acc0, acc1, acc2, acc3;
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wire [31:0] acc0, acc1, acc2, acc3;
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reg [7:0] volume; // master volume
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reg [3:0] volume; // master volume
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wire [11:0] tg1_o,tg2_o,tg3_o,tg4_o; // tone generator output
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wire [11:0] tg1_o,tg2_o,tg3_o,tg4_o; // tone generator output
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wire [7:0] env; // envelope generator output
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wire [7:0] env; // envelope generator output
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wire [7:0] env3;
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wire [7:0] env0, env1, env2, env3;
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wire [19:0] out0,out1,out2,out3;
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wire [19:0] out0,out1,out2,out3;
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wire [2:0] es0,es1,es2,es3;
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wire [2:0] es0,es1,es2,es3;
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wire [29:0] out4;
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wire [29:0] out4;
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reg [21:0] sum,fsum;
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reg [21:0] sum,fsum;
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reg [21:0] sum2;
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reg [21:0] sum2;
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wire [21:0] filtin1; // FIR filter input
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wire [21:0] filtin1; // FIR filter input
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wire [37:0] filt_o; // FIR filter output
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wire [37:0] filt_o; // FIR filter output
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reg [1:0] cnt;
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reg [1:0] cnt;
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reg [1:0] cnt1,cnt2,cnt3;
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reg [1:0] cnt1,cnt2,cnt3;
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// channel select signal
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// channel select signal
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wire [1:0] sel = cnt[1:0];
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wire [1:0] sel = cnt[1:0];
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and(cs, cyc_i, stb_i, cs_i);
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and(cs, cyc_i, stb_i, cs_i);
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reg ack1,ack2;
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reg ack1,ack2;
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always @(posedge clk_i)
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always @(posedge clk_i)
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ack1 <= cs;
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ack1 <= cs;
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always @(posedge clk_i)
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always @(posedge clk_i)
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ack2 <= ack1 & cs;
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ack2 <= ack1 & cs;
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assign ack_o = cs ? (we_i ? 1'b1 : ack2) : 1'b0;
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assign ack_o = cs ? (we_i ? 1'b1 : ack2) : 1'b0;
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// Register shadow ram for register readback
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// Register shadow ram for register readback
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reg [15:0] reg_shadow [63:0];
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reg [15:0] reg_shadow [63:0];
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reg [8:0] radr;
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reg [8:0] radr;
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always @(posedge clk_i)
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always @(posedge clk_i)
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if (cs & we_i) reg_shadow[adr_i[7:2]] <= dat_i[15:0];
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if (cs & we_i) reg_shadow[adr_i[7:2]] <= dat_i[15:0];
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always @(posedge clk_i)
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always @(posedge clk_i)
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radr <= adr_i[7:2];
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radr <= adr_i[7:2];
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wire [15:0] reg_shadow_o = reg_shadow[radr];
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wire [15:0] reg_shadow_o = reg_shadow[radr];
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// write to registers
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// write to registers
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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if (rst_i) begin
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if (rst_i) begin
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freq0 <= 0;
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freq0 <= 0;
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freq1 <= 0;
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freq1 <= 0;
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freq2 <= 0;
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freq2 <= 0;
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freq3 <= 0;
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freq3 <= 0;
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pw0 <= 0;
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pw0 <= 0;
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pw1 <= 0;
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pw1 <= 0;
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pw2 <= 0;
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pw2 <= 0;
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pw3 <= 0;
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pw3 <= 0;
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test <= 0;
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test <= 0;
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vt[0] <= 0;
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vt[0] <= 0;
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vt[1] <= 0;
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vt[1] <= 0;
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vt[2] <= 0;
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vt[2] <= 0;
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vt[3] <= 0;
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vt[3] <= 0;
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gate <= 0;
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gate <= 0;
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outctrl <= 0;
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outctrl <= 0;
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filt <= 0;
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filt <= 0;
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attack0 <= 0;
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attack0 <= 0;
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attack1 <= 0;
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attack1 <= 0;
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attack2 <= 0;
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attack2 <= 0;
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attack3 <= 0;
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attack3 <= 0;
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decay0 <= 0;
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decay0 <= 0;
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sustain0 <= 0;
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sustain0 <= 0;
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relese0 <= 0;
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relese0 <= 0;
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decay1 <= 0;
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decay1 <= 0;
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sustain1 <= 0;
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sustain1 <= 0;
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relese1 <= 0;
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relese1 <= 0;
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decay2 <= 0;
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decay2 <= 0;
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sustain2 <= 0;
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sustain2 <= 0;
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relese2 <= 0;
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relese2 <= 0;
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decay3 <= 0;
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decay3 <= 0;
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sustain3 <= 0;
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sustain3 <= 0;
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relese3 <= 0;
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relese3 <= 0;
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sync <= 0;
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sync <= 0;
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ringmod <= 0;
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ringmod <= 0;
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volume <= 0;
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volume <= 0;
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end
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end
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else begin
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else begin
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if (cs & we_i) begin
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if (cs & we_i) begin
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case(adr_i[7:2])
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case(adr_i[7:2])
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//---------------------------------------------------------
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//---------------------------------------------------------
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6'd00: freq0 <= dat_i[23:0];
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6'd00: freq0 <= dat_i[23:0];
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6'd01: pw0 <= dat_i[15:0];
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6'd01: pw0 <= dat_i[15:0];
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6'd02: begin
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6'd02: begin
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vt[0] <= dat_i[6:2];
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vt[0] <= dat_i[7:2];
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outctrl[0] <= dat_i[8];
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outctrl[0] <= dat_i[8];
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filt[0] <= dat_i[9];
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filt[0] <= dat_i[9];
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eg[0] <= dat_i[10];
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gate[0] <= dat_i[12];
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gate[0] <= dat_i[12];
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sync[0] <= dat_i[13];
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sync[0] <= dat_i[13];
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ringmod[0] <= dat_i[14];
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ringmod[0] <= dat_i[14];
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test[0] <= dat_i[15];
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test[0] <= dat_i[15];
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end
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end
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6'd03: begin
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6'd03: attack0 <= dat_i[23:0];
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attack0 <= dat_i[31:16];
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6'd04: decay0 <= dat_i[23:0];
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decay0 <= dat_i[15:0];
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6'd05: sustain0 <= dat_i[7:0];
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end
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6'd06: relese0 <= dat_i[23:0];
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6'd04: begin
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6'd07: wtadr0 <= {dat_i[13:1],1'b0};
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relese0 <= dat_i[15:0];
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sustain0 <= dat_i[23:16];
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end
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6'd05: wtadr0 <= {dat_i[13:1],1'b0};
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//---------------------------------------------------------
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//---------------------------------------------------------
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6'd06: freq1 <= dat_i[23:0];
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6'd08: freq1 <= dat_i[23:0];
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6'd07: pw1 <= dat_i[15:0];
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6'd09: pw1 <= dat_i[15:0];
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6'd08: begin
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6'd10: begin
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vt[1] <= dat_i[6:2];
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vt[1] <= dat_i[7:2];
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outctrl[1] <= dat_i[8];
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outctrl[1] <= dat_i[8];
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filt[1] <= dat_i[9];
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filt[1] <= dat_i[9];
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eg[1] <= dat_i[10];
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gate[1] <= dat_i[12];
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gate[1] <= dat_i[12];
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sync[1] <= dat_i[13];
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sync[1] <= dat_i[13];
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ringmod[1] <= dat_i[14];
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ringmod[1] <= dat_i[14];
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test[1] <= dat_i[15];
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test[1] <= dat_i[15];
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end
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end
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6'd09: begin
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6'd11: attack1 <= dat_i[23:0];
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attack1 <= dat_i[31:16];
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6'd12: decay1 <= dat_i[23:0];
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decay1 <= dat_i[15:0];
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6'd13: sustain1 <= dat_i[7:0];
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end
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6'd14: relese1 <= dat_i[23:0];
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6'd10:
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6'd15: wtadr1 <= {dat_i[13:1],1'b0};
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begin
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relese1 <= dat_i[15:0];
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sustain1 <= dat_i[23:16];
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end
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6'd11: wtadr1 <= {dat_i[13:1],1'b0};
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//---------------------------------------------------------
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//---------------------------------------------------------
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6'd12: freq2 <= dat_i[23:0];
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6'd16: freq2 <= dat_i[23:0];
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6'd13: pw2 <= dat_i[15:0];
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6'd17: pw2 <= dat_i[15:0];
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6'd14: begin
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6'd18: begin
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vt[2] <= dat_i[6:2];
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vt[2] <= dat_i[7:2];
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outctrl[2] <= dat_i[8];
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outctrl[2] <= dat_i[8];
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filt[2] <= dat_i[9];
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filt[2] <= dat_i[9];
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eg[2] <= dat_i[10];
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gate[2] <= dat_i[12];
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gate[2] <= dat_i[12];
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sync[2] <= dat_i[5];
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sync[2] <= dat_i[5];
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outctrl[0] <= dat_i[13];
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outctrl[0] <= dat_i[13];
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ringmod[2] <= dat_i[14];
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ringmod[2] <= dat_i[14];
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test[2] <= dat_i[15];
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test[2] <= dat_i[15];
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end
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end
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6'd15: begin
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6'd19: attack2 <= dat_i[23:0];
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attack2 <= dat_i[31:16];
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6'd20: decay2 <= dat_i[23:0];
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decay2 <= dat_i[15:0];
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6'd21: sustain2 <= dat_i[7:0];
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end
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6'd22: relese2 <= dat_i[23:0];
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6'd16: begin
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6'd23: wtadr2 <= {dat_i[13:1],1'b0};
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relese2 <= dat_i[15:0];
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sustain2 <= dat_i[23:16];
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end
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6'd17: wtadr1 <= {dat_i[13:1],1'b0};
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//---------------------------------------------------------
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//---------------------------------------------------------
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6'd18: freq3 <= dat_i[23:0];
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6'd24: freq3 <= dat_i[23:0];
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6'd19: pw3 <= dat_i[15:0];
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6'd25: pw3 <= dat_i[15:0];
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6'd20: begin
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6'd26: begin
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vt[3] <= dat_i[6:2];
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vt[3] <= dat_i[7:2];
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outctrl[3] <= dat_i[8];
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outctrl[3] <= dat_i[8];
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filt[3] <= dat_i[9];
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filt[3] <= dat_i[9];
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eg[3] <= dat_i[10];
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gate[3] <= dat_i[12];
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gate[3] <= dat_i[12];
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sync[3] <= dat_i[13];
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sync[3] <= dat_i[13];
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ringmod[3] <= dat_i[14];
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ringmod[3] <= dat_i[14];
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test[3] <= dat_i[15];
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test[3] <= dat_i[15];
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end
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end
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6'd21: begin
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6'd27: attack3 <= dat_i[23:0];
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attack3 <= dat_i[31:16];
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6'd28: decay3 <= dat_i[23:0];
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decay3 <= dat_i[15:0];
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6'd29: sustain3 <= dat_i[7:0];
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relese3 <= dat_i[15:0];
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6'd30: relese3 <= dat_i[23:0];
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sustain3 <= dat_i[23:16];
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6'd31: wtadr3 <= {dat_i[13:1],1'b0};
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end
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6'd22: wtadr1 <= {dat_i[13:1],1'b0};
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//---------------------------------------------------------
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//---------------------------------------------------------
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6'd44: volume <= dat_i[7:0];
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6'd44: volume <= dat_i[3:0];
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default: ;
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default: ;
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endcase
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endcase
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end
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end
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end
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end
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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case(adr_i[7:2])
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case(adr_i[7:2])
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6'd45: begin
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6'd45: begin
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dat_o <= acc3;
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dat_o <= acc3;
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end
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end
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6'd45: begin
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6'd46: begin
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dat_o <= {24'h0,env3};
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dat_o <= {24'h0,env3};
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end
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end
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6'd46: dat_o <= {17'h0,es3,1'b0,es2,1'b0,es1,1'b0,es0};
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6'd47: dat_o <= {17'h0,es3,1'b0,es2,1'b0,es1,1'b0,es0};
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default: begin
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default: begin
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dat_o <= reg_shadow_o;
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dat_o <= reg_shadow_o;
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end
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end
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endcase
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endcase
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wire [13:0] madr;
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wire [13:0] madr;
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mux4to1 #(12) u11
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mux4to1 #(12) u11
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(
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(
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.e(1'b1),
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.e(1'b1),
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.s(cnt),
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.s(cnt),
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.i0(wtadr0 + {acc0[27:17],1'b0}),
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.i0(wtadr0 + {acc0[27:17],1'b0}),
|
.i1(wtadr1 + {acc1[27:17],1'b0}),
|
.i1(wtadr1 + {acc1[27:17],1'b0}),
|
.i2(wtadr2 + {acc2[27:17],1'b0}),
|
.i2(wtadr2 + {acc2[27:17],1'b0}),
|
.i3(wtadr3 + {acc3[27:17],1'b0}),
|
.i3(wtadr3 + {acc3[27:17],1'b0}),
|
.z(madr)
|
.z(madr)
|
);
|
);
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
m_adr_o <= madr;
|
m_adr_o <= madr;
|
|
wire [11:0] wave_i = m_dat_i;
|
|
|
// This counter controls channel multiplexing for the wave table
|
// This counter controls channel multiplexing for the wave table
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
if (rst_i)
|
if (rst_i)
|
cnt <= 2'd0;
|
cnt <= 2'd0;
|
else
|
else
|
cnt <= cnt + 2'd1;
|
cnt <= cnt + 2'd1;
|
|
|
// note generator - multi-channel
|
// note generator - multi-channel
|
PSGToneGenerator u1a
|
PSGToneGenerator u1a
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.ack(cnt==2'b11),
|
.ack(cnt==2'b11),
|
.test(test[0]),
|
.test(test[0]),
|
.vt(vt[0]),
|
.vt(vt[0]),
|
.freq(freq0),
|
.freq(freq0),
|
.pw(pw0),
|
.pw(pw0),
|
.acc(acc0),
|
.acc(acc0),
|
.prev_acc(acc3),
|
.prev_acc(acc3),
|
.wave(wave_i),
|
.wave(wave_i),
|
.sync(sync[0]),
|
.sync(sync[0]),
|
.ringmod(ringmod[0]),
|
.ringmod(ringmod[0]),
|
.o(tg1_o)
|
.o(tg1_o)
|
);
|
);
|
|
|
PSGToneGenerator u1b
|
PSGToneGenerator u1b
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.ack(cnt==2'b00),
|
.ack(cnt==2'b00),
|
.test(test[1]),
|
.test(test[1]),
|
.vt(vt[1]),
|
.vt(vt[1]),
|
.freq(freq1),
|
.freq(freq1),
|
.pw(pw1),
|
.pw(pw1),
|
.acc(acc1),
|
.acc(acc1),
|
.prev_acc(acc0),
|
.prev_acc(acc0),
|
.wave(wave_i),
|
.wave(wave_i),
|
.sync(sync[1]),
|
.sync(sync[1]),
|
.ringmod(ringmod[1]),
|
.ringmod(ringmod[1]),
|
.o(tg2_o)
|
.o(tg2_o)
|
);
|
);
|
|
|
PSGToneGenerator u1c
|
PSGToneGenerator u1c
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.ack(cnt==2'b01),
|
.ack(cnt==2'b01),
|
.test(test[2]),
|
.test(test[2]),
|
.vt(vt[2]),
|
.vt(vt[2]),
|
.freq(freq2),
|
.freq(freq2),
|
.pw(pw2),
|
.pw(pw2),
|
.acc(acc2),
|
.acc(acc2),
|
.prev_acc(acc1),
|
.prev_acc(acc1),
|
.wave(wave_i),
|
.wave(wave_i),
|
.sync(sync[2]),
|
.sync(sync[2]),
|
.ringmod(ringmod[2]),
|
.ringmod(ringmod[2]),
|
.o(tg3_o)
|
.o(tg3_o)
|
);
|
);
|
|
|
PSGToneGenerator u1d
|
PSGToneGenerator u1d
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.ack(cnt==2'b10),
|
.ack(cnt==2'b10),
|
.test(test[3]),
|
.test(test[3]),
|
.vt(vt[3]),
|
.vt(vt[3]),
|
.freq(freq3),
|
.freq(freq3),
|
.pw(pw3),
|
.pw(pw3),
|
.acc(acc3),
|
.acc(acc3),
|
.prev_acc(acc2),
|
.prev_acc(acc2),
|
.wave(wave_i),
|
.wave(wave_i),
|
.sync(sync[3]),
|
.sync(sync[3]),
|
.ringmod(ringmod[3]),
|
.ringmod(ringmod[3]),
|
.o(tg4_o)
|
.o(tg4_o)
|
);
|
);
|
|
|
PSGEnvelopeGenerator u2a
|
PSGEnvelopeGenerator u2a
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.gate(gate[0]),
|
.gate(gate[0]),
|
.attack(attack0),
|
.attack(attack0),
|
.decay(decay0),
|
.decay(decay0),
|
.sustain(sustain0),
|
.sustain(sustain0),
|
.relese(relese0),
|
.relese(relese0),
|
.o(env0),
|
.o(env0),
|
.envState(es0)
|
.envState(es0)
|
);
|
);
|
|
|
PSGEnvelopeGenerator u2b
|
PSGEnvelopeGenerator u2b
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.gate(gate[1]),
|
.gate(gate[1]),
|
.attack(attack1),
|
.attack(attack1),
|
.decay(decay1),
|
.decay(decay1),
|
.sustain(sustain1),
|
.sustain(sustain1),
|
.relese(relese1),
|
.relese(relese1),
|
.o(env1),
|
.o(env1),
|
.envState(es1)
|
.envState(es1)
|
);
|
);
|
|
|
PSGEnvelopeGenerator u2c
|
PSGEnvelopeGenerator u2c
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.gate(gate[2]),
|
.gate(gate[2]),
|
.attack(attack2),
|
.attack(attack2),
|
.decay(decay2),
|
.decay(decay2),
|
.sustain(sustain2),
|
.sustain(sustain2),
|
.relese(relese2),
|
.relese(relese2),
|
.o(env2),
|
.o(env2),
|
.envState(es2)
|
.envState(es2)
|
);
|
);
|
|
|
PSGEnvelopeGenerator u2d
|
PSGEnvelopeGenerator u2d
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.gate(gate[3]),
|
.gate(gate[3]),
|
.attack(attack3),
|
.attack(attack3),
|
.decay(decay3),
|
.decay(decay3),
|
.sustain(sustain3),
|
.sustain(sustain3),
|
.relese(relese3),
|
.relese(relese3),
|
.o(env3),
|
.o(env3),
|
.envState(es3)
|
.envState(es3)
|
);
|
);
|
|
|
// shape output according to envelope
|
// shape output according to envelope
|
PSGShaper u5a
|
PSGShaper u5a
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce(1'b1),
|
.ce(1'b1),
|
.tgi(tg1_o),
|
.tgi(tg1_o),
|
.env(env0),
|
.env(eg[0] ? env0 : 8'hFF),
|
.o(out0)
|
.o(out0)
|
);
|
);
|
|
|
PSGShaper u5b
|
PSGShaper u5b
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce(1'b1),
|
.ce(1'b1),
|
.tgi(tg2_o),
|
.tgi(tg2_o),
|
.env(env1),
|
.env(eg[1] ? env1 : 8'hFF),
|
.o(out1)
|
.o(out1)
|
);
|
);
|
|
|
PSGShaper u5c
|
PSGShaper u5c
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce(1'b1),
|
.ce(1'b1),
|
.tgi(tg3_o),
|
.tgi(tg3_o),
|
.env(env2),
|
.env(eg[2] ? env2 : 8'hFF),
|
.o(out2)
|
.o(out2)
|
);
|
);
|
|
|
PSGShaper u5d
|
PSGShaper u5d
|
(
|
(
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.ce(1'b1),
|
.ce(1'b1),
|
.tgi(tg4_o),
|
.tgi(tg4_o),
|
.env(env3),
|
.env(eg[3] ? env3 : 8'hFF),
|
.o(out3)
|
.o(out3)
|
);
|
);
|
|
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
cnt1 <= cnt;
|
cnt1 <= cnt;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
cnt2 <= cnt1;
|
cnt2 <= cnt1;
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
cnt3 <= cnt2;
|
cnt3 <= cnt2;
|
|
|
// Sum the channels not going to the filter
|
// Sum the channels not going to the filter
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
sum <=
|
sum <=
|
{2'd0,(out0 & {20{outctrl[0]}})} +
|
{2'd0,(out0 & {20{outctrl[0]}})} +
|
{2'd0,(out1 & {20{outctrl[1]}})} +
|
{2'd0,(out1 & {20{outctrl[1]}})} +
|
{2'd0,(out2 & {20{outctrl[2]}})} +
|
{2'd0,(out2 & {20{outctrl[2]}})} +
|
{2'd0,(out3 & {20{outctrl[3]}})};
|
{2'd0,(out3 & {20{outctrl[3]}})};
|
|
|
// Sum the channels going to the filter
|
// Sum the channels going to the filter
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
fsum <=
|
fsum <=
|
{2'd0,(out0 & {20{filt[0]}})} +
|
{2'd0,(out0 & {20{filt[0]}})} +
|
{2'd0,(out1 & {20{filt[1]}})} +
|
{2'd0,(out1 & {20{filt[1]}})} +
|
{2'd0,(out2 & {20{filt[2]}})} +
|
{2'd0,(out2 & {20{filt[2]}})} +
|
{2'd0,(out3 & {20{filt[3]}})};
|
{2'd0,(out3 & {20{filt[3]}})};
|
|
|
// The FIR filter
|
// The FIR filter
|
PSGFilter2 u8
|
PSGFilter2 u8
|
(
|
(
|
.rst(rst_i),
|
.rst(rst_i),
|
.clk(clk_i),
|
.clk(clk_i),
|
.cnt(cnt2),
|
.cnt(cnt2),
|
.wr(we_i && stb_i && adr_i[7:6]==3'b11),
|
.wr(we_i && stb_i && adr_i[7:6]==3'b11),
|
.adr(adr_i[5:2]),
|
.adr(adr_i[5:2]),
|
.din({dat_i[15],dat_i[11:0]}),
|
.din({dat_i[15],dat_i[11:0]}),
|
.i(fsum),
|
.i(fsum),
|
.o(filt_o)
|
.o(filt_o)
|
);
|
);
|
|
|
// Sum the filtered and unfiltered output
|
// Sum the filtered and unfiltered output
|
always @(posedge clk_i)
|
always @(posedge clk_i)
|
sum2 <= sum + filt_o[37:16];
|
sum2 <= sum + filt_o[37:16];
|
|
|
// Last stage:
|
// Last stage:
|
// Adjust output according to master volume
|
// Adjust output according to master volume
|
PSGVolumeControl u10
|
PSGVolumeControl u10
|
(
|
(
|
.rst_i(rst_i),
|
.rst_i(rst_i),
|
.clk_i(clk_i),
|
.clk_i(clk_i),
|
.i(sum2),
|
.i(sum2),
|
.volume(volume),
|
.volume(volume),
|
.o(out4)
|
.o(out4)
|
);
|
);
|
|
|
assign o = out4[29:12];
|
assign o = out4[29:12];
|
|
|
endmodule
|
endmodule
|
|
|
