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Line 47... |
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module PSGEnvelopeGenerator(rst, clk, gate, attack, decay, sustain, relese, o, envState);
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module PSGEnvelopeGenerator(rst, clk, gate, attack, decay, sustain, relese, o, envState);
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input rst; // reset
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input rst; // reset
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input clk; // core clock
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input clk; // core clock
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input gate;
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input gate;
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input [15:0] attack;
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input [23:0] attack;
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input [15:0] decay;
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input [23:0] decay;
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input [7:0] sustain; // sustain level
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input [7:0] sustain; // sustain level
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input [15:0] relese;
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input [23:0] relese;
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output [7:0] o;
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output [7:0] o;
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output [2:0] envState;
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output [2:0] envState;
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// envelope generator states
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// envelope generator states
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parameter ENV_IDLE = 3'd0;
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parameter ENV_IDLE = 3'd0;
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// Per channel count storage
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// Per channel count storage
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reg [7:0] envCtr;
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reg [7:0] envCtr;
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reg [7:0] envCtr2;
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reg [7:0] envCtr2;
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reg [7:0] iv; // interval value for decay/release
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reg [7:0] iv; // interval value for decay/release
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reg [2:0] icnt; // interval count
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reg [2:0] icnt; // interval count
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reg [19:0] envDvn;
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reg [27:0] envDvn;
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reg [2:0] envState;
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reg [2:0] envState;
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reg [2:0] envStateNxt;
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reg [2:0] envStateNxt;
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reg [15:0] envStepPeriod; // determines the length of one step of the envelope generator
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reg [23:0] envStepPeriod; // determines the length of one step of the envelope generator
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integer n;
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integer n;
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wire attack_next = envState==ENV_IDLE && gate;
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wire attack_next = envState==ENV_IDLE && gate;
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wire decay_next = envState==ENV_ATTACK && envCtr==8'hFE && sustain != 8'hFF;
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wire decay_next = envState==ENV_ATTACK && envCtr==8'hFE && sustain != 8'hFF;
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Line 145... |
end
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end
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ENV_ATTACK:
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ENV_ATTACK:
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begin
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begin
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icnt <= 1;
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icnt <= 1;
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iv <= (8'hff - sustain) >> 3;
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iv <= (8'hff - sustain) >> 3;
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if (envDvn==20'h0) begin
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if (envDvn==28'h0) begin
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envCtr2 <= 0;
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envCtr2 <= 0;
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envCtr <= envCtr + 1;
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envCtr <= envCtr + 1;
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end
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end
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end
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end
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ENV_DECAY,
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ENV_DECAY,
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ENV_RELEASE:
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ENV_RELEASE:
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if (envDvn==20'h0) begin
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if (envDvn==28'h0) begin
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envCtr <= envCtr - 1;
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envCtr <= envCtr - 1;
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if (envCtr2==iv) begin
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if (envCtr2==iv) begin
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envCtr2 <= 0;
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envCtr2 <= 0;
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if (icnt < 3'd7)
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if (icnt < 3'd7)
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icnt <= icnt + 1;
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icnt <= icnt + 1;
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begin
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begin
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case(envState)
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case(envState)
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ENV_ATTACK: envStepPeriod <= attack;
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ENV_ATTACK: envStepPeriod <= attack;
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ENV_DECAY: envStepPeriod <= decay;
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ENV_DECAY: envStepPeriod <= decay;
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ENV_RELEASE: envStepPeriod <= relese;
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ENV_RELEASE: envStepPeriod <= relese;
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default: envStepPeriod <= 16'h0;
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default: envStepPeriod <= 24'h0;
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endcase
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endcase
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end
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end
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// double the delay at appropriate points
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// double the delay at appropriate points
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// for exponential modelling
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// for exponential modelling
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wire [19:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt;
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wire [27:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt;
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// handle the clock divider
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// handle the clock divider
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// loadable down counter
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// loadable down counter
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// This sets the period of each step of the envelope
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// This sets the period of each step of the envelope
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casex({attack_next,decay_next,release_next})
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casex({attack_next,decay_next,release_next})
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3'b1xx: envDvn <= {4'h0,attack};
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3'b1xx: envDvn <= {4'h0,attack};
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3'b01x: envDvn <= {4'h0,decay};
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3'b01x: envDvn <= {4'h0,decay};
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3'b001: envDvn <= {4'h0,relese};
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3'b001: envDvn <= {4'h0,relese};
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default:
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default:
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if (envDvn==20'h0)
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if (envDvn==28'h0)
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envDvn <= envStepPeriod1;
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envDvn <= envStepPeriod1;
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else
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else
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envDvn <= envDvn - 1;
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envDvn <= envDvn - 1;
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endcase
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endcase
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end
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end
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