`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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// ============================================================================
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// ============================================================================
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// __
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// __
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// \\__/ o\ (C) 2007-2017 Robert Finch, Waterloo
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// \\__/ o\ (C) 2007-2017 Robert Finch, Waterloo
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// \ __ / All rights reserved.
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// \ __ / All rights reserved.
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// \/_// robfinch<remove>@finitron.ca
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// \/_// robfinch<remove>@finitron.ca
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// ||
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// ||
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//
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//
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// PSGEnvelopeGenerator.v
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// PSGEnvelopeGenerator.v
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This source file is distributed in the hope that it will be useful,
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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// GNU General Public License for more details.
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//
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//
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// You should have received a copy of the GNU General Public License
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//
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//=============================================================================
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//=============================================================================
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/*
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/*
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sample attack values / rates
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sample attack values / rates
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----------------------------
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----------------------------
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8 2ms
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8 2ms
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32 8ms
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32 8ms
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64 16ms
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64 16ms
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96 24ms
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96 24ms
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152 38ms
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152 38ms
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224 56ms
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224 56ms
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272 68ms
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272 68ms
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320 80ms
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320 80ms
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400 100ms
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400 100ms
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955 239ms
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955 239ms
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1998 500ms
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1998 500ms
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3196 800ms
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3196 800ms
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3995 1s
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3995 1s
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12784 3.2s
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12784 3.2s
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21174 5.3s
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21174 5.3s
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31960 8s
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31960 8s
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rate = 990.00ns x 256 x value
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rate = 990.00ns x 256 x value
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*/
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*/
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module PSGEnvelopeGenerator(rst, clk, gate, attack, decay, sustain, relese, o, envState);
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module PSGEnvelopeGenerator(rst, clk, gate, attack, decay, sustain, relese, o, envState);
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input rst; // reset
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input rst; // reset
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input clk; // core clock
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input clk; // core clock
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input gate;
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input gate;
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input [15:0] attack;
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input [23:0] attack;
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input [15:0] decay;
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input [23:0] decay;
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input [7:0] sustain; // sustain level
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input [7:0] sustain; // sustain level
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input [15:0] relese;
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input [23:0] relese;
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output [7:0] o;
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output [7:0] o;
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output [2:0] envState;
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output [2:0] envState;
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// envelope generator states
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// envelope generator states
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parameter ENV_IDLE = 3'd0;
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parameter ENV_IDLE = 3'd0;
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parameter ENV_ATTACK = 3'd1;
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parameter ENV_ATTACK = 3'd1;
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parameter ENV_DECAY = 3'd2;
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parameter ENV_DECAY = 3'd2;
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parameter ENV_SUSTAIN = 3'd3;
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parameter ENV_SUSTAIN = 3'd3;
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parameter ENV_RELEASE = 3'd4;
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parameter ENV_RELEASE = 3'd4;
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// Per channel count storage
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// Per channel count storage
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reg [7:0] envCtr;
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reg [7:0] envCtr;
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reg [7:0] envCtr2;
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reg [7:0] envCtr2;
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reg [7:0] iv; // interval value for decay/release
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reg [7:0] iv; // interval value for decay/release
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reg [2:0] icnt; // interval count
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reg [2:0] icnt; // interval count
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reg [19:0] envDvn;
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reg [27:0] envDvn;
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reg [2:0] envState;
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reg [2:0] envState;
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reg [2:0] envStateNxt;
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reg [2:0] envStateNxt;
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reg [15:0] envStepPeriod; // determines the length of one step of the envelope generator
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reg [23:0] envStepPeriod; // determines the length of one step of the envelope generator
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integer n;
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integer n;
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wire attack_next = envState==ENV_IDLE && gate;
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wire attack_next = envState==ENV_IDLE && gate;
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wire decay_next = envState==ENV_ATTACK && envCtr==8'hFE && sustain != 8'hFF;
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wire decay_next = envState==ENV_ATTACK && envCtr==8'hFE && sustain != 8'hFF;
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wire release_next = envState==ENV_SUSTAIN && !gate;
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wire release_next = envState==ENV_SUSTAIN && !gate;
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// Envelope generate state machine
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// Envelope generate state machine
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// Determine the next envelope state
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// Determine the next envelope state
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always @*
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always @*
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begin
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begin
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envStateNxt <= envState; // default to hold state
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envStateNxt <= envState; // default to hold state
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case (envState)
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case (envState)
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ENV_IDLE:
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ENV_IDLE:
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if (gate)
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if (gate)
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envStateNxt <= ENV_ATTACK;
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envStateNxt <= ENV_ATTACK;
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ENV_ATTACK:
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ENV_ATTACK:
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if (envCtr==8'hFE) begin
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if (envCtr==8'hFE) begin
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if (sustain==8'hFF)
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if (sustain==8'hFF)
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envStateNxt <= ENV_SUSTAIN;
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envStateNxt <= ENV_SUSTAIN;
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else
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else
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envStateNxt <= ENV_DECAY;
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envStateNxt <= ENV_DECAY;
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end
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end
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ENV_DECAY:
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ENV_DECAY:
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if (envCtr==sustain)
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if (envCtr==sustain)
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envStateNxt <= ENV_SUSTAIN;
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envStateNxt <= ENV_SUSTAIN;
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ENV_SUSTAIN:
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ENV_SUSTAIN:
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if (~gate)
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if (~gate)
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envStateNxt <= ENV_RELEASE;
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envStateNxt <= ENV_RELEASE;
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ENV_RELEASE:
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ENV_RELEASE:
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if (envCtr==8'h00)
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if (envCtr==8'h00)
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envStateNxt <= ENV_IDLE;
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envStateNxt <= ENV_IDLE;
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else if (gate)
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else if (gate)
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envStateNxt <= ENV_SUSTAIN;
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envStateNxt <= ENV_SUSTAIN;
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// In case of hardware problem
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// In case of hardware problem
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default:
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default:
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envStateNxt <= ENV_IDLE;
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envStateNxt <= ENV_IDLE;
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endcase
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endcase
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end
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end
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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envState <= ENV_IDLE;
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envState <= ENV_IDLE;
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else
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else
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envState <= envStateNxt;
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envState <= envStateNxt;
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// Handle envelope counter
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// Handle envelope counter
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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envCtr <= 0;
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envCtr <= 0;
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envCtr2 <= 0;
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envCtr2 <= 0;
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icnt <= 1;
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icnt <= 1;
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iv <= 0;
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iv <= 0;
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end
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end
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else begin
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else begin
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case (envState)
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case (envState)
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ENV_IDLE:
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ENV_IDLE:
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begin
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begin
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envCtr <= 0;
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envCtr <= 0;
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envCtr2 <= 0;
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envCtr2 <= 0;
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icnt <= 1;
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icnt <= 1;
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iv <= 0;
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iv <= 0;
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end
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end
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ENV_SUSTAIN:
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ENV_SUSTAIN:
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begin
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begin
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envCtr2 <= 0;
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envCtr2 <= 0;
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icnt <= 1;
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icnt <= 1;
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iv <= sustain >> 3;
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iv <= sustain >> 3;
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end
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end
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ENV_ATTACK:
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ENV_ATTACK:
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begin
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begin
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icnt <= 1;
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icnt <= 1;
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iv <= (8'hff - sustain) >> 3;
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iv <= (8'hff - sustain) >> 3;
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if (envDvn==20'h0) begin
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if (envDvn==28'h0) begin
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envCtr2 <= 0;
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envCtr2 <= 0;
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envCtr <= envCtr + 1;
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envCtr <= envCtr + 1;
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end
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end
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end
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end
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ENV_DECAY,
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ENV_DECAY,
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ENV_RELEASE:
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ENV_RELEASE:
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if (envDvn==20'h0) begin
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if (envDvn==28'h0) begin
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envCtr <= envCtr - 1;
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envCtr <= envCtr - 1;
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if (envCtr2==iv) begin
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if (envCtr2==iv) begin
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envCtr2 <= 0;
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envCtr2 <= 0;
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if (icnt < 3'd7)
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if (icnt < 3'd7)
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icnt <= icnt + 1;
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icnt <= icnt + 1;
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end
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end
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else
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else
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envCtr2 <= envCtr2 + 1;
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envCtr2 <= envCtr2 + 1;
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end
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end
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endcase
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endcase
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end
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end
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// Determine envelope divider adjustment source
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// Determine envelope divider adjustment source
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always @*
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always @*
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begin
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begin
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case(envState)
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case(envState)
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ENV_ATTACK: envStepPeriod <= attack;
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ENV_ATTACK: envStepPeriod <= attack;
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ENV_DECAY: envStepPeriod <= decay;
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ENV_DECAY: envStepPeriod <= decay;
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ENV_RELEASE: envStepPeriod <= relese;
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ENV_RELEASE: envStepPeriod <= relese;
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default: envStepPeriod <= 16'h0;
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default: envStepPeriod <= 24'h0;
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endcase
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endcase
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end
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end
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// double the delay at appropriate points
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// double the delay at appropriate points
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// for exponential modelling
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// for exponential modelling
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wire [19:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt;
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wire [27:0] envStepPeriod1 = {4'b0,envStepPeriod} << icnt;
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// handle the clock divider
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// handle the clock divider
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// loadable down counter
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// loadable down counter
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// This sets the period of each step of the envelope
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// This sets the period of each step of the envelope
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always @(posedge clk)
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always @(posedge clk)
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if (rst)
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if (rst)
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envDvn <= 0;
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envDvn <= 0;
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else begin
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else begin
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casex({attack_next,decay_next,release_next})
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casex({attack_next,decay_next,release_next})
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3'b1xx: envDvn <= {4'h0,attack};
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3'b1xx: envDvn <= {4'h0,attack};
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3'b01x: envDvn <= {4'h0,decay};
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3'b01x: envDvn <= {4'h0,decay};
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3'b001: envDvn <= {4'h0,relese};
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3'b001: envDvn <= {4'h0,relese};
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default:
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default:
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if (envDvn==20'h0)
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if (envDvn==28'h0)
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envDvn <= envStepPeriod1;
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envDvn <= envStepPeriod1;
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else
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else
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envDvn <= envDvn - 1;
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envDvn <= envDvn - 1;
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endcase
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endcase
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end
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end
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assign o = envCtr;
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assign o = envCtr;
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endmodule
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endmodule
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