--! @file memblock.vhd
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--! @file memblock.vhd
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--! @brief Bloque de memoria.
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--! @brief Bloque de memoria.
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- memblock.vhd
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-- memblock.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity memblock is
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entity memblock is
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generic (
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generic (
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width : integer := 32;
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width : integer := 32;
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blocksize : integer := 512;
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blocksize : integer := 512;
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widthadmemblock : integer :=9;
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widthadmemblock : integer :=9;
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external_writeable_blocks : integer := 12;
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external_writeable_blocks : integer := 12;
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external_readable_blocks : integer := 8;
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external_readable_blocks : integer := 8;
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external_readable_widthad : integer := 3;
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external_readable_widthad : integer := 3;
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external_writeable_widthad : integer := 4
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external_writeable_widthad : integer := 4
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);
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);
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port (
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port (
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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ext_rd,ext_wr,int_wr,int_rd : in std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad+widthadmemblock-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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ext_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_wr_add : in std_logic_vector(widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add, int_wr_add : in std_logic_vector(widthadmemblock-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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);
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);
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end memblock;
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end memblock;
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architecture memblock_arch of memblock is
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architecture memblock_arch of memblock is
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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component scfifo
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component scfifo
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generic (
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generic (
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add_ram_output_register :string;
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add_ram_output_register :string;
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intended_device_family :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_showahead :string;
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lpm_type :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_width :natural;
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lpm_widthu :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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overflow_checking :string;
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underflow_checking :string;
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underflow_checking :string;
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use_eab :string
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use_eab :string
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);
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);
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port(
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port(
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rdreq : in std_logic;
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rdreq : in std_logic;
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aclr : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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clock : in std_logic;
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clock : in std_logic;
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q : out std_logic_vector(width-1 downto 0);
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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wrreq : in std_logic;
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data : in std_logic_vector(width-1 downto 0);
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data : in std_logic_vector(lpm_width-1 downto 0);
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full : out std_logic
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full : out std_logic
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);
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);
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end component;
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end component;
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component altsyncram
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component altsyncram
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generic (
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generic (
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address_aclr_b : string;
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address_aclr_b : string;
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address_reg_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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intended_device_family : string;
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lpm_type : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_a : natural;
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numwords_b : natural;
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numwords_b : natural;
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operation_mode : string;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_a : natural;
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widthad_b : natural;
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widthad_b : natural;
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width_a : natural;
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width_a : natural;
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width_b : natural;
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width_b : natural;
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width_byteena_a : natural
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width_byteena_a : natural
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);
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);
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port (
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port (
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wren_a : in std_logic;
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wren_a : in std_logic;
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clock0 : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(widthad_a-1 downto 0);
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address_a : in std_logic_vector(widthad_a-1 downto 0);
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address_b : in std_logic_vector(widthad_b-1 downto 0);
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address_b : in std_logic_vector(widthad_b-1 downto 0);
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rden_b : in std_logic;
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rden_b : in std_logic;
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q_b : out std_logic_vector(width-1 downto 0);
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q_b : out std_logic_vector(width-1 downto 0);
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data_a : in std_logic_vector(width-1 downto 0)
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data_a : in std_logic_vector(width-1 downto 0)
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);
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);
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end component;
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end component;
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1 downto 0);
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signal s0ext_rd_add_one_hot : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_wr_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_wr_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0ext_wr : std_logic;
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signal s0ext_wr : std_logic;
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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signal s1ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s1ext_q,sint_d : vectorblock08;
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signal sint_rd_add : vectorblock02;
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signal s1int_q : vectorblock12;
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begin
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begin
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dpfifo : scfifo
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dpfifo : scfifo
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",width*2,4,"OFF","OFF","ON")
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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normfifo : scfifo
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normfifo : scfifo
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",width*3,5,"OFF","OFF","ON")
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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mblocks:
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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results_blocks:
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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resultsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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port map (ext_rd,clk,int_wr_add,ext_rd_add(widthadmemblock-1 downto 0),'1',s1ext_q(i),sint_d(i));
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end generate results_blocks;
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1);
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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generic port(s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0), s0int_rd_add, int_rd, , memblock_q);
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add(i/6),'1',s1int_q(i),s0ext_d);
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end generate mblocks;
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end generate operands_blocks;
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process (clk)
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operands_block_proc: process (clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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--! Registro de entrada
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--! Registro
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s0ext_wr_add <= ext_wr_add;
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s0ext_wr_add <= ext_wr_add;
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s0ext_wr <= ext_wr;
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s0ext_wr <= ext_wr;
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s0ext_d <= ext_d;
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--! Etapa 0: Decodificacion de las señ:ales de escritura.
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case s0ext_wr_add((external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
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case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
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when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
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when x"0" => s0ext_wr_add_one_hot <= x"00"&"000"&s0ext_wr;
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when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
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when x"1" => s0ext_wr_add_one_hot <= x"00"&"00"&s0ext_wr&'0';
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when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
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when x"2" => s0ext_wr_add_one_hot <= x"00"&'0'&s0ext_wr&"00";
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when x"3" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
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when x"3" => s0ext_wr_add_one_hot <= x"00"&s0ext_wr&"000";
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when x"4" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
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when x"4" => s0ext_wr_add_one_hot <= x"0"&"000"&s0ext_wr&x"0";
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when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
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when x"5" => s0ext_wr_add_one_hot <= x"0"&"00"&s0ext_wr&'0'&x"0";
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when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
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when x"6" => s0ext_wr_add_one_hot <= x"0"&'0'&s0ext_wr&"00"&x"0";
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when x"7" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
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when x"7" => s0ext_wr_add_one_hot <= x"0"&s0ext_wr&"000"&x"0";
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when x"8" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
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when x"8" => s0ext_wr_add_one_hot <= "000"&s0ext_wr&x"00";
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when x"9" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
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when x"9" => s0ext_wr_add_one_hot <= "00"&s0ext_wr&'0'&x"00";
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when x"A" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
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when x"A" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"00"&x"00";
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when x"B" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
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when others => s0ext_wr_add_one_hot <= s0ext_wr&"000"&x"00";
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when others => s0ext_wr_add_one_hot <= s0ext_wr&x"000";
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end case;
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end case;
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case ('0'&s0ext_rd_add) is
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end if;
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when x"0" => s0ext_rd_add_one_hot <= x"0"&"000"&ext_rd;
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end process;
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when x"1" => s0ext_rd_add_one_hot <= x"0"&"00"&ext_rd&'0';
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results_block_proc: process(clk)
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when x"2" => s0ext_rd_add_one_hot <= x"0"&'0'&ext_rd&"00";
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begin
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when x"3" => s0ext_rd_add_one_hot <= x"0"&ext_rd&"000";
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if clk'event and clk='1' then
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when x"4" => s0ext_rd_add_one_hot <= "000"&ext_rd&x"0";
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--!Registrar entrada
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when x"5" => s0ext_rd_add_one_hot <= "00"&ext_rd&'0'&x"0";
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s0ext_rd_add <= ext_rd_add(external_readable_widthad+widthadmemblock-1 downto widthadmemblock);
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when x"6" => s0ext_rd_add_one_hot <= '0'&ext_rd&"00"&x"0";
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--!Etapa 0: Leer memorias
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when others => s0ext_rd_add_one_hot <= ext_rd&"000"&x"0";
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s1ext_rd_add <= s0ext_rd_add;
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--!Etapa 1: Seleccionar dato a leer;
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case '0'&s1ext_rd_add is
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when x"0" => ext_q <= s1ext_q(0);
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when x"1" => ext_q <= s1ext_q(1);
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when x"2" => ext_q <= s1ext_q(2);
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when x"3" => ext_q <= s1ext_q(3);
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when x"4" => ext_q <= s1ext_q(4);
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when x"5" => ext_q <= s1ext_q(5);
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when x"6" => ext_q <= s1ext_q(6);
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when others => ext_q <= s1ext_q(7);
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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end memblock_arch;
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end memblock_arch;
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