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Line 138... |
signal sint_rd_add : vectorblock02;
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signal sint_rd_add : vectorblock02;
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signal s1int_q : vectorblock12;
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signal s1int_q : vectorblock12;
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begin
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begin
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dpfifo : scfifo
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dpfifo : scfifo --! Debe ir registrada la salida.
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",9,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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generic map ("ON","Cyclone III","RAM_BLOCK_TYPE=M9K",15,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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normfifo : scfifo
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normfifo : scfifo
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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generic map ("OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",26,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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instrfifo : scififo
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instrfifo : scififo
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