--! @file memblock.vhd
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--! @file memblock.vhd
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--! @brief Bloque de memoria.
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--! @brief Bloque de memoria.
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--! @author Julián Andrés Guarín Reyes
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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--------------------------------------------------------------
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-- RAYTRAC
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- Author Julian Andres Guarin
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-- memblock.vhd
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-- memblock.vhd
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-- This file is part of raytrac.
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-- This file is part of raytrac.
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--
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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--
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity memblock is
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entity memblock is
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generic (
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generic (
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width : integer := 32;
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width : integer := 32;
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blocksize : integer := 512;
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blocksize : integer := 512;
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widthadmemblock : integer :=9;
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widthadmemblock : integer :=9;
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external_writeable_blocks : integer := 12;
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external_writeable_blocks : integer := 12;
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external_readable_blocks : integer := 8;
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external_readable_blocks : integer := 8;
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external_readable_widthad : integer := 3;
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external_readable_widthad : integer := 3;
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external_writeable_widthad : integer := 4
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external_writeable_widthad : integer := 4
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);
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);
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port (
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port (
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clk,ena,dpfifo_flush,normfifo_flush,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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clk,rst,dpfifo_rd,normfifo_rd,dpfifo_wr,normfifo_wr : in std_logic;
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dpfifo_empty, normfifo_empty, dpfifo_full, normfifo_full : out std_logic;
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instrfifo_rd,instrfifo_wr,resultfifo_wr: in std_logic;
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instrfifo_flush,instrfifo_rd,instrfifo_wr,resultfifo_flush,resultfifo_wr: in std_logic;
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instrfifo_empty: out std_logic;
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instrfifo_empty,instrfifo_full: out std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_rd,ext_wr: in std_logic;
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_wr_add : in std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_rd_add : in std_logic_vector(external_readable_widthad-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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ext_d: in std_logic_vector(width-1 downto 0);
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--!sresultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
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resultfifo_full,resultfifo_empty : out std_logic_vector(external_readable_blocks-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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int_d : in std_logic_vector(external_readable_blocks*width-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
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ext_q,instrfifo_q : out std_logic_vector(width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_q : out std_logic_vector(external_writeable_blocks*width-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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int_rd_add : in std_logic_vector(2*widthadmemblock-1 downto 0);
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instrfifo_d : in std_logic_vector(width-1 downto 0);
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instrfifo_d : in std_logic_vector(width-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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dpfifo_d : in std_logic_vector(width*2-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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normfifo_d : in std_logic_vector(width*3-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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dpfifo_q : out std_logic_vector(width*2-1 downto 0);
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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normfifo_q : out std_logic_vector(width*3-1 downto 0)
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);
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);
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end memblock;
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end memblock;
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architecture memblock_arch of memblock is
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architecture memblock_arch of memblock is
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock12 is array (11 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock08 is array (07 downto 0) of std_logic_vector(width-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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type vectorblock02 is array (01 downto 0) of std_logic_vector(widthadmemblock-1 downto 0);
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constant rstMasterValue : std_logic := '0';
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component scfifo
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component scfifo
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generic (
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generic (
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add_ram_output_register :string;
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add_ram_output_register :string;
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almost_full_value :natural;
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almost_full_value :natural;
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allow_wrcycle_when_full :string;
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allow_wrcycle_when_full :string;
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intended_device_family :string;
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intended_device_family :string;
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lpm_hint :string;
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lpm_hint :string;
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lpm_numwords :natural;
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lpm_numwords :natural;
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lpm_showahead :string;
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lpm_showahead :string;
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lpm_type :string;
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lpm_type :string;
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lpm_width :natural;
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lpm_width :natural;
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lpm_widthu :natural;
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lpm_widthu :natural;
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overflow_checking :string;
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overflow_checking :string;
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underflow_checking :string;
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underflow_checking :string;
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use_eab :string
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use_eab :string
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);
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);
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port(
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port(
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rdreq : in std_logic;
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rdreq : in std_logic;
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aclr : in std_logic;
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aclr : in std_logic;
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empty : out std_logic;
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empty : out std_logic;
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clock : in std_logic;
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clock : in std_logic;
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q : out std_logic_vector(lpm_width-1 downto 0);
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q : out std_logic_vector(lpm_width-1 downto 0);
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wrreq : in std_logic;
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wrreq : in std_logic;
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data : in std_logic_vector(lpm_width-1 downto 0);
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data : in std_logic_vector(lpm_width-1 downto 0);
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almost_full : out std_logic;
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almost_full : out std_logic;
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full : out std_logic
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full : out std_logic
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);
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);
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end component;
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end component;
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component altsyncram
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component altsyncram
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generic (
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generic (
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address_aclr_b : string;
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address_aclr_b : string;
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address_reg_b : string;
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address_reg_b : string;
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clock_enable_input_a : string;
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clock_enable_input_a : string;
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clock_enable_input_b : string;
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clock_enable_input_b : string;
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clock_enable_output_b : string;
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clock_enable_output_b : string;
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intended_device_family : string;
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intended_device_family : string;
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lpm_type : string;
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lpm_type : string;
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numwords_a : natural;
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numwords_a : natural;
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numwords_b : natural;
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numwords_b : natural;
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operation_mode : string;
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operation_mode : string;
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outdata_aclr_b : string;
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outdata_aclr_b : string;
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outdata_reg_b : string;
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outdata_reg_b : string;
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power_up_uninitialized : string;
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power_up_uninitialized : string;
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ram_block_type : string;
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ram_block_type : string;
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rdcontrol_reg_b : string;
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rdcontrol_reg_b : string;
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read_during_write_mode_mixed_ports : string;
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read_during_write_mode_mixed_ports : string;
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widthad_a : natural;
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widthad_a : natural;
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widthad_b : natural;
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widthad_b : natural;
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width_a : natural;
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width_a : natural;
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width_b : natural;
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width_b : natural;
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width_byteena_a : natural
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width_byteena_a : natural
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);
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);
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port (
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port (
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wren_a : in std_logic;
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wren_a : in std_logic;
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clock0 : in std_logic;
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clock0 : in std_logic;
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address_a : in std_logic_vector(widthad_a-1 downto 0);
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address_a : in std_logic_vector(widthad_a-1 downto 0);
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address_b : in std_logic_vector(widthad_b-1 downto 0);
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address_b : in std_logic_vector(widthad_b-1 downto 0);
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rden_b : in std_logic;
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rden_b : in std_logic;
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q_b : out std_logic_vector(width-1 downto 0);
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q_b : out std_logic_vector(width-1 downto 0);
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data_a : in std_logic_vector(width-1 downto 0)
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data_a : in std_logic_vector(width-1 downto 0)
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);
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);
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end component;
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end component;
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add_one_hot : std_logic_vector(external_writeable_blocks-1+1 downto 0); --! La se ñal extra es para la escritura de la cola de instrucciones.
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_wr_add : std_logic_vector(external_writeable_widthad+widthadmemblock-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0ext_rd_add : std_logic_vector(external_readable_widthad-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0int_rd_add : std_logic_vector(widthadmemblock-1 downto 0);
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_wr,s0ext_rd : std_logic;
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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signal s0ext_d : std_logic_vector(width-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_rd_ack : std_logic_vector(external_readable_blocks-1 downto 0);
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signal s0ext_q,sint_d : vectorblock08;
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signal s0ext_q,sint_d : vectorblock08;
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signal sint_rd_add : vectorblock02;
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signal sint_rd_add : vectorblock02;
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signal s1int_q : vectorblock12;
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signal s1int_q : vectorblock12;
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begin
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begin
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--! Cola interna de producto punto, ubicada entre el pipe line aritméco.
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--! Cola interna de producto punto, ubicada entre el pipe line aritméco.
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q0q1 : scfifo --! Debe ir registrada la salida.
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q0q1 : scfifo --! Debe ir registrada la salida.
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generic map ("ON",8,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",16,"OFF","SCFIFO",64,4,"OFF","OFF","ON")
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generic map (
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port map (dpfifo_rd,dpfifo_flush,dpfifo_empty,clk,dpfifo_q,dpfifo_wr,dpfifo_d,dpfifo_full);
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add_ram_output_register => "OFF",
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "CycloneIII",
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lpm_hint => "RAM_BLOCK_TYPE=M9K",
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almost_full_value => 8,
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lpm_numwords => 8,
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lpm_showahead => "ON",
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lpm_type => "SCIFIFO",
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lpm_width => 64,
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lpm_widthu => 3,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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port map (
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rdreq => dpfifo_rd,
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aclr => '0',
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empty => open,
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clock => clk,
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q => dpfifo_q,
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wrreq => dpfifo_wr,
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data => dpfifo_d
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);
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmé
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmé
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qxqyqz : scfifo
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qxqyqz : scfifo
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generic map ("ON",23,"OFF","Cyclone III","RAM_BLOCK_TYPE=M9K",32,"OFF","SCFIFO",96,5,"OFF","OFF","ON")
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generic map (
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port map (normfifo_rd,normfifo_flush,normfifo_empty,clk,normfifo_q,normfifo_wr,normfifo_d,normfifo_full);
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add_ram_output_register => "OFF",
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "Cyclone III",
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lpm_hint => "RAM_BLOCK_TYPE=M9K",
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almost_full_value => 32,
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lpm_numwords => 32,
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lpm_showahead => "ON",
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lpm_type => "SCFIFO",
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lpm_width => 96,
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lpm_widthu => 5,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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port map (
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rdreq => normfifo_rd,
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aclr => '0',
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empty => open,
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clock => clk,
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q => normfifo_q,
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wrreq => normfifo_wr,
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data => normfifo_d,
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almost_full => open,
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full => open
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);
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--! Cola de instrucciones
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--! Cola de instrucciones
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qi : scfifo
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qi : scfifo
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generic map ("ON",31,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",32,"OFF","SCIFIFO",32,5,"ON","OFF","ON")
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generic map (
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port map (instrfifo_rd,instrfifo_flush,instrfifo_empty,clk,instrfifo_q,instrfifo_wr,instrfifo_d,instrfifo_full);
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add_ram_output_register => "OFF",
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "Cyclone III",
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lpm_hint => "RAM_BLOCK_TYPE=M9K",
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almost_full_value => 32,
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lpm_numwords => 32,
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lpm_showahead => "OFF",
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lpm_type => "SCIFIFO",
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lpm_width => 32,
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lpm_widthu => 5,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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port map (
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rdreq => instrfifo_rd,
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aclr => '0',
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empty => instrfifo_empty,
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clock => clk,
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q => instrfifo_q,
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wrreq => instrfifo_wr,
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data => instrfifo_d,
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almost_full => open
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);
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--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
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--! Conectar los registros de lectura interna del bloque de operandos a los arreglos > abstracció:n de código, no influye en la sintesis del circuito.
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (0)<= int_rd_add(widthadmemblock-1 downto 0);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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sint_rd_add (1)<= int_rd_add(2*widthadmemblock-1 downto widthadmemblock);
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--! Instanciación de la cola de resultados.
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results_blocks:
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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resultsfifo : scfifo
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generic map ("ON",511,"ON","Cyclone III","RAM_BLOCK_TYPE_M9K",512,"OFF","SCIFIFO",32,9,"ON","OFF","ON")
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port map (s0ext_rd_ack(i),resultfifo_flush,resultfifo_empty(i),clk,s0ext_q(i),resultfifo_wr,sint_d(i),open,sresultfifo_full(i));
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end generate results_blocks;
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--! Instanciación de la cola de resultados de salida.
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--! Instanciación de la cola de resultados de salida.
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operands_blocks:
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operands_blocks:
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for i in 11 downto 0 generate
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for i in 11 downto 0 generate
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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int_q((i+1)*width-1 downto width*i) <= s1int_q(i);
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operandsblock : altsyncram
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operandsblock : altsyncram
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generic map ("NONE","CLOCK0","BYPASS","BYPASS","BYPASS","Cyclone III","altsyncram",2**widthadmemblock,2**widthadmemblock,"DUAL_PORT","NONE","CLOCK0","FALSE","M9K","CLOCK0","OLD_DATA",widthadmemblock,widthadmemblock,width,width,1)
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generic map (
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port map (s0ext_wr_add_one_hot(i),clk,s0ext_wr_add(widthadmemblock-1 downto 0),sint_rd_add((i/3) mod 2),'1',s1int_q(i),s0ext_d);
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address_aclr_b => "NONE",
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address_reg_b => "CLOCK0",
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clock_enable_input_a => "BYPASS",
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clock_enable_input_b => "BYPASS",
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clock_enable_output_b => "BYPASS",
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intended_device_family => "Cyclone III",
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lpm_type => "altsyncram",
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numwords_a => 2**widthadmemblock,
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numwords_b => 2**widthadmemblock,
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operation_mode => "DUAL_PORT",
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outdata_aclr_b => "NONE",
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outdata_reg_b => "CLOCK0",
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power_up_uninitialized => "FALSE",
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ram_block_type => "M9K",
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rdcontrol_reg_b => "CLOCK0",
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read_during_write_mode_mixed_ports => "OLD_DATA",
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widthad_a => widthadmemblock,
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widthad_b => widthadmemblock,
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width_a => width,
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width_b => width,
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width_byteena_a => 1
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)
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port map (
|
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wren_a => s0ext_wr_add_one_hot(i),
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clock0 => clk,
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address_a => s0ext_wr_add(widthadmemblock-1 downto 0),
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address_b => sint_rd_add((i/3) mod 2),
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rden_b => '1',
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q_b => s1int_q(i),
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data_a => s0ext_d
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);
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end generate operands_blocks;
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end generate operands_blocks;
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|
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--! Instanciación de la cola de resultados.
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results_blocks:
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for i in 7 downto 0 generate
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sint_d(i) <= int_d((i+1)*width-1 downto i*width);
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resultsfifo : scfifo
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generic map (
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add_ram_output_register => "OFF",
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almost_full_value => 480,
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allow_wrcycle_when_full => "OFF",
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intended_device_family => "Cyclone III",
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lpm_hint => "RAM_BLOCK_TYPE=M9K",
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lpm_numwords => 512,
|
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lpm_showahead => "ON",
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lpm_type => "SCIFIFO",
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lpm_width => 32,
|
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lpm_widthu => 9,
|
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overflow_checking => "ON",
|
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underflow_checking => "ON",
|
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use_eab => "ON"
|
|
)
|
|
port map (
|
|
rdreq => s0ext_rd_ack(i),
|
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aclr => '0',
|
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empty => resultfifo_empty(i),
|
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clock => clk,
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q => s0ext_q(i),
|
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wrreq => resultfifo_wr,
|
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data => sint_d(i),
|
|
almost_full => resultfifo_full(i),
|
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full => open
|
|
);
|
|
end generate results_blocks;
|
|
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--! Escritura en registros de operandos de entrada.
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--! Escritura en registros de operandos de entrada.
|
operands_block_proc: process (clk,ena)
|
operands_block_proc: process (clk,rst)
|
begin
|
begin
|
if clk'event and clk='1' and ena='1' then
|
if rst=rstMasterValue then
|
|
s0ext_wr_add <= (others => '0');
|
|
s0ext_wr <= '0';
|
|
s0ext_d <= (others => '0');
|
|
elsif clk'event and clk='1' then
|
--! Registro de entrada
|
--! Registro de entrada
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s0ext_wr_add <= ext_wr_add;
|
s0ext_wr_add <= ext_wr_add;
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s0ext_wr <= ext_wr;
|
s0ext_wr <= ext_wr;
|
s0ext_d <= ext_d;
|
s0ext_d <= ext_d;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.
|
--! Decodificación de señal escritura x bloque de memoria, selecciona la memoria en la que se va a escribir a partir de la dirección de entrada.
|
operands_block_comb: process (s0ext_wr_add,s0ext_wr)
|
operands_block_comb: process (s0ext_wr_add,s0ext_wr)
|
begin
|
begin
|
|
|
--! Etapa 0: Decodificacion de las señ:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.
|
--! Etapa 0: Decodificacion de las señ:ales de escritura.Revisar el capitulo de bloques de memoria para chequear como está el pool de direcciones por bloques de vectores.
|
--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
|
--! Las direcciones de bloque 3,7,11,15 corresponden a la cola de instrucciones.
|
case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
|
case s0ext_wr_add(external_writeable_widthad+widthadmemblock-1 downto widthadmemblock) is
|
when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
|
when x"0" => s0ext_wr_add_one_hot <= '0'&x"00"&"000"&s0ext_wr;
|
when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
|
when x"1" => s0ext_wr_add_one_hot <= '0'&x"00"&"00"&s0ext_wr&'0';
|
when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
|
when x"2" => s0ext_wr_add_one_hot <= '0'&x"00"&'0'&s0ext_wr&"00";
|
when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
|
when x"4" => s0ext_wr_add_one_hot <= '0'&x"00"&s0ext_wr&"000";
|
when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
|
when x"5" => s0ext_wr_add_one_hot <= '0'&x"0"&"000"&s0ext_wr&x"0";
|
when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
|
when x"6" => s0ext_wr_add_one_hot <= '0'&x"0"&"00"&s0ext_wr&'0'&x"0";
|
when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
|
when x"8" => s0ext_wr_add_one_hot <= '0'&x"0"&'0'&s0ext_wr&"00"&x"0";
|
when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
|
when x"9" => s0ext_wr_add_one_hot <= '0'&x"0"&s0ext_wr&"000"&x"0";
|
when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
|
when x"A" => s0ext_wr_add_one_hot <= '0'&"000"&s0ext_wr&x"00";
|
when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
|
when x"C" => s0ext_wr_add_one_hot <= '0'&"00"&s0ext_wr&'0'&x"00";
|
when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
|
when x"D" => s0ext_wr_add_one_hot <= '0'&'0'&s0ext_wr&"00"&x"00";
|
when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
|
when x"E" => s0ext_wr_add_one_hot <= '0'&s0ext_wr&"000"&x"00";
|
when others => s0ext_wr_add_one_hot <= '1'&x"000";
|
when others => s0ext_wr_add_one_hot <= '1'&x"000";
|
end case;
|
end case;
|
|
|
end process;
|
end process;
|
|
|
--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.
|
--! Decodificación para seleccionar que cola de resultados se conectar´ a la salida del RayTrac.
|
results_block_proc: process(clk,ena)
|
results_block_proc: process(clk,rst)
|
begin
|
begin
|
if clk'event and clk='1' and ena='1' then
|
if rst=rstMasterValue then
|
|
s0ext_rd_add <= (others => '0');
|
|
s0ext_rd <= '0';
|
|
elsif clk'event and clk='1' then
|
--!Registrar entrada
|
--!Registrar entrada
|
s0ext_rd_add <= ext_rd_add;
|
s0ext_rd_add <= ext_rd_add;
|
s0ext_rd <= ext_rd;
|
s0ext_rd <= ext_rd;
|
--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
|
--!Etapa 0: Decodificar la cola que se va a mover (rdack! fifo showahead mode) y por ende leer ese dato.
|
case '0'&s0ext_rd_add is
|
case '0'&s0ext_rd_add is
|
when x"0" => ext_q <= s0ext_q(0);
|
when x"0" => ext_q <= s0ext_q(0);
|
when x"1" => ext_q <= s0ext_q(1);
|
when x"1" => ext_q <= s0ext_q(1);
|
when x"2" => ext_q <= s0ext_q(2);
|
when x"2" => ext_q <= s0ext_q(2);
|
when x"3" => ext_q <= s0ext_q(3);
|
when x"3" => ext_q <= s0ext_q(3);
|
when x"4" => ext_q <= s0ext_q(4);
|
when x"4" => ext_q <= s0ext_q(4);
|
when x"5" => ext_q <= s0ext_q(5);
|
when x"5" => ext_q <= s0ext_q(5);
|
when x"6" => ext_q <= s0ext_q(6);
|
when x"6" => ext_q <= s0ext_q(6);
|
when others => ext_q <= s0ext_q(7);
|
when others => ext_q <= s0ext_q(7);
|
end case;
|
end case;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
--! rdack decoder para las colas de resultados de salida.
|
--! rdack decoder para las colas de resultados de salida.
|
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
|
results_block_proc_combinatorial_stage: process(s0ext_rd,s0ext_rd_add)
|
begin
|
begin
|
case '0'&s0ext_rd_add is
|
case '0'&s0ext_rd_add is
|
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
|
when x"0" => s0ext_rd_ack <= x"0"&"000"&s0ext_rd;
|
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
|
when x"1" => s0ext_rd_ack <= x"0"&"00"&s0ext_rd&'0';
|
when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
|
when x"2" => s0ext_rd_ack <= x"0"&"0"&s0ext_rd&"00";
|
when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
|
when x"3" => s0ext_rd_ack <= x"0"&s0ext_rd&"000";
|
when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
|
when x"4" => s0ext_rd_ack <= "000"&s0ext_rd&x"0";
|
when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
|
when x"5" => s0ext_rd_ack <= "00"&s0ext_rd&'0'&x"0";
|
when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
|
when x"6" => s0ext_rd_ack <= "0"&s0ext_rd&"00"&x"0";
|
when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
|
when others => s0ext_rd_ack <= s0ext_rd&"000"&x"0";
|
end case;
|
end case;
|
end process;
|
end process;
|
end memblock_arch;
|
end memblock_arch;
|
|
|
|
|
