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[/] [raytrac/] [branches/] [fp/] [memblock.vhd] - Diff between revs 159 and 160

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Rev 159 Rev 160
Line 69... Line 69...
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
        signal s0ext_d                          : std_logic_vector(floatwidth-1 downto 0);
        --!TBXEND
        --!TBXEND
        --! Señal de soporte
        --! Señal de soporte
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
        signal s0ext_wr_add_choice      : std_logic_vector(3 downto 0);
 
 
        --!TBXSTART:MEMBLOCK_EXTERNAL_READ
        --!TXBXSTART:MEMBLOCK_EXTERNAL_READ
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
        signal s0ext_rd_add                     : std_logic_vector(2 downto 0);
        signal s0ext_rd                         : std_logic;
        signal s0ext_rd                         : std_logic;
        signal s0ext_rd_ack                     : std_logic_vector(8-1 downto 0);
        signal s0ext_rd_ack                     : std_logic_vector(8-1 downto 0);
        signal s0ext_q                          : vectorblock08;
        signal s0ext_q                          : vectorblock08;
        --!TBXEND
        --!TBXEND
Line 85... Line 85...
        signal s0int_rd_add                     : std_logic_vector(widthadmemblock-1 downto 0);
        signal s0int_rd_add                     : std_logic_vector(widthadmemblock-1 downto 0);
        signal sint_rd_add                      : vectorblockadd02;
        signal sint_rd_add                      : vectorblockadd02;
        signal s1int_q                          : vectorblock12;
        signal s1int_q                          : vectorblock12;
        --!TBXEND
        --!TBXEND
 
 
        --!TBXSTART:MEMBLOCK_INTERNAL_WRITE
        --!TXBXSTART:MEMBLOCK_INTERNAL_WRITE
        signal sint_d                           : vectorblock08;
        signal sint_d                           : vectorblock08;
        signal sresultfifo_full         : std_logic_vector(7 downto 0);
        signal sresultfifo_full         : std_logic_vector(7 downto 0);
        --!TBXEND
        --!TBXEND
 
 
begin
begin
Line 157... Line 157...
                allow_rwcycle_when_full => "OFF",
                allow_rwcycle_when_full => "OFF",
                intended_device_family  => "Cyclone III",
                intended_device_family  => "Cyclone III",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                lpm_hint                                => "RAM_BLOCK_TYPE=M9K",
                almost_full_value               => 32,
                almost_full_value               => 32,
                lpm_numwords                    => 32,
                lpm_numwords                    => 32,
                lpm_showahead                   => "OFF",
                lpm_showahead                   => "ON",
                lpm_type                                => "SCIFIFO",
                lpm_type                                => "SCIFIFO",
                lpm_width                               => 32,
                lpm_width                               => 32,
                lpm_widthu                              => 5,
                lpm_widthu                              => 5,
                overflow_checking               => "ON",
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                underflow_checking              => "ON",

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