--! @file raytrac.vhd
|
--! @file raytrac.vhd
|
--! @brief Archivo con el RTL que describe al RayTrac en su totalidad.
|
--! @brief Archivo con el RTL que describe al RayTrac en su totalidad.
|
|
|
--! @author Julián Andrés Guarín Reyes
|
--! @author Julián Andrés Guarín Reyes
|
--------------------------------------------------------------
|
--------------------------------------------------------------
|
-- RAYTRAC
|
-- RAYTRAC
|
-- Author Julian Andres Guarin
|
-- Author Julian Andres Guarin
|
-- Rytrac.vhd
|
-- Rytrac.vhd
|
-- This file is part of raytrac.
|
-- This file is part of raytrac.
|
--
|
--
|
-- raytrac is free software: you can redistribute it and/or modify
|
-- raytrac is free software: you can redistribute it and/or modify
|
-- it under the terms of the GNU General Public License as published by
|
-- it under the terms of the GNU General Public License as published by
|
-- the Free Software Foundation, either version 3 of the License, or
|
-- the Free Software Foundation, either version 3 of the License, or
|
-- (at your option) any later version.
|
-- (at your option) any later version.
|
--
|
--
|
-- raytrac is distributed in the hope that it will be useful,
|
-- raytrac is distributed in the hope that it will be useful,
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
--
|
--
|
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
|
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use work.arithpack.all;
|
use work.arithpack.all;
|
|
|
entity raytrac is
|
entity raytrac is
|
port (
|
port (
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
|
|
--! Señal de lectura de alguna de las colas de resultados.
|
--! Señal de lectura de alguna de las colas de resultados.
|
rd : in std_logic;
|
rd : in std_logic;
|
|
|
--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
|
--! Señal de escritura en alguno de los bloques de memoria de operandos o en la cola de instrucciones.
|
wr : in std_logic;
|
wr : in std_logic;
|
|
|
--! Direccion de escritura o lectura
|
--! Direccion de escritura o lectura
|
add : in std_logic_vector (12 downto 0);
|
add : in std_logic_vector (12 downto 0);
|
|
|
--! datos de entrada
|
--! datos de entrada
|
d : in std_logic_vector (31 downto 0);
|
d : in std_logic_vector (31 downto 0);
|
|
|
--! Interrupciones
|
--! Interrupciones
|
int : out std_logic;
|
irq : out std_logic;
|
|
|
--! Salidas
|
--! Salidas
|
q : out std_logic_vector (31 downto 0)
|
q : out std_logic_vector (31 downto 0)
|
|
|
|
|
|
|
);
|
);
|
end entity;
|
end entity;
|
|
|
architecture raytrac_arch of raytrac is
|
architecture raytrac_arch of raytrac is
|
|
|
--! Señales de State Machine -> Memblock
|
--! Señales de State Machine -> Memblock
|
--!TBXSTART:SM
|
--!TBXSTART:SM
|
signal s_int_rd_add : std_logic_vector (17 downto 0);
|
signal s_int_rd_add : std_logic_vector (17 downto 0);
|
signal s_adda : std_logic_vector (8 downto 0);
|
signal s_adda : std_logic_vector (8 downto 0);
|
signal s_addb : std_logic_vector (8 downto 0);
|
signal s_addb : std_logic_vector (8 downto 0);
|
signal s_iq_rd_ack : std_logic;
|
signal s_iq_rd_ack : std_logic;
|
--! Señales de State Machine -> DataPathControl
|
--! Señales de State Machine -> DataPathControl
|
signal s_sync_chain_0 : std_logic;
|
signal s_sync_chain_0 : std_logic;
|
signal s_dpc_uca : std_logic_vector(2 downto 0);
|
signal s_dpc_uca : std_logic_vector(2 downto 0);
|
signal s_eoi : std_logic;
|
signal s_eoi : std_logic;
|
signal s_sign : std_logic;
|
signal s_sign : std_logic;
|
--!TBXEND
|
--!TBXEND
|
--! Señales de State Machine -> Testbench
|
--! Señales de State Machine -> Testbench
|
signal s_smState : macState;
|
signal s_smState : macState;
|
|
|
|
|
|
|
|
|
|
|
|
|
--!TBXSTART:MBLK
|
--!TBXSTART:MBLK
|
--! Señales de Memblock -> State Machine
|
--! Señales de Memblock -> State Machine
|
signal s_iq_empty : std_logic;
|
signal s_iq_empty : std_logic;
|
signal s_iq : std_logic_vector (31 downto 0);
|
signal s_iq : std_logic_vector (31 downto 0);
|
--! Señales de Memblock -> Interruption Machine
|
--! Señales de Memblock -> Interruption Machine
|
signal s_rfull_events : std_logic_vector (3 downto 0); --Estas señales tambien entran a DPC.
|
signal s_rfull_events : std_logic_vector (3 downto 0); --Estas señales tambien entran a DPC.
|
--! Señales de Memblock -> DPC.
|
--! Señales de Memblock -> DPC.
|
signal s_q : vectorblock12;
|
signal s_q : vectorblock12;
|
signal s_normfifo_q : std_logic_vector (3*32-1 downto 0);
|
signal s_normfifo_q : std_logic_vector (3*32-1 downto 0);
|
signal s_dpfifo_q : std_logic_vector (2*32-1 downto 0);
|
signal s_dpfifo_q : std_logic_vector (2*32-1 downto 0);
|
--!TBXEND
|
--!TBXEND
|
--!TXBXSTART:SQR32
|
--!TXBXSTART:SQR32
|
--!Señales de Bloque de Raíz Cuadrada a DPC
|
--!Señales de Bloque de Raíz Cuadrada a DPC
|
signal s_sq32 : std_logic_vector (31 downto 0);
|
signal s_sq32 : std_logic_vector (31 downto 0);
|
--!TBXEND
|
--!TBXEND
|
--!TXBXSTART:INV32
|
--!TXBXSTART:INV32
|
--!Señales del bloque inversor a DPC.
|
--!Señales del bloque inversor a DPC.
|
signal s_qout32 : std_logic_vector (31 downto 0);
|
signal s_qout32 : std_logic_vector (31 downto 0);
|
--!TBXEND
|
--!TBXEND
|
--!TXBXSTART:DPC
|
--!TXBXSTART:DPC
|
--! Señales de DataPathControl -> State Machine
|
--! Señales de DataPathControl -> State Machine
|
signal s_full_r : std_logic;
|
signal s_full_r : std_logic;
|
--! Señales de DPC a sqrt32.
|
--! Señales de DPC a sqrt32.
|
signal s_rd32 : std_logic_vector (31 downto 0);
|
signal s_rd32 : std_logic_vector (31 downto 0);
|
--! Señales de DPC a inv32.
|
--! Señales de DPC a inv32.
|
signal s_dvd32 : std_logic_vector (31 downto 0);
|
signal s_dvd32 : std_logic_vector (31 downto 0);
|
--! Señales de DPC a invr32.
|
--! Señales de DPC a invr32.
|
--! Señ que va desde DPC -> Memblock
|
--! Señ que va desde DPC -> Memblock
|
signal s_resultfifo_wr : std_logic_vector (7 downto 0);
|
signal s_resultfifo_wr : std_logic_vector (7 downto 0);
|
signal s_dpfifo_w : std_logic;
|
signal s_dpfifo_w : std_logic;
|
signal s_dpfifo_r : std_logic;
|
signal s_dpfifo_r : std_logic;
|
signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
|
signal s_dpfifo_d : std_logic_vector (2*32-1 downto 0);
|
signal s_normfifo_w : std_logic;
|
signal s_normfifo_w : std_logic;
|
signal s_normfifo_r : std_logic;
|
signal s_normfifo_r : std_logic;
|
signal s_results_d : vectorblock08;
|
signal s_results_d : vectorblock08;
|
signal s_normfifo_d : std_logic_vector (3*32-1 downto 0);
|
signal s_normfifo_d : std_logic_vector (3*32-1 downto 0);
|
--!Señales de DPC a Interruption Machine
|
--!Señales de DPC a Interruption Machine
|
signal s_eoi_events : std_logic_vector (3 downto 0);
|
signal s_eoi_events : std_logic_vector (3 downto 0);
|
--! Señales de DPC a ArithBlock
|
--! Señales de DPC a ArithBlock
|
signal s_f : vectorblock12;
|
signal s_f : vectorblock12;
|
signal s_a : vectorblock08;
|
signal s_a : vectorblock08;
|
--! Parcialmente las señales de salida de los sumadores van al data path control.
|
--! Parcialmente las señales de salida de los sumadores van al data path control.
|
signal s_s : vectorblock04;
|
signal s_s : vectorblock04;
|
signal s_p : vectorblock06;
|
signal s_p : vectorblock06;
|
--!TBXEND
|
--!TBXEND
|
signal s_resultsfifo_w : std_logic_vector (4 downto 0);
|
signal s_resultsfifo_w : std_logic_vector (4 downto 0);
|
|
|
--!TBXSTART:IM
|
--!TBXSTART:IM
|
--! Señales de Interruption Machine al testbench
|
--! Señales de Interruption Machine al testbench
|
signal s_iCtrlState : iCtrlState;
|
signal s_iCtrlState : iCtrlState;
|
signal s_int : std_logic;
|
signal s_int : std_logic;
|
--!TBXEND
|
--!TBXEND
|
begin
|
begin
|
|
|
--! Sacar las interrupciones
|
--! Sacar las interrupciones
|
int <= s_int;
|
irq <= s_int;
|
|
|
--! Signo de los bloques de suma
|
--! Signo de los bloques de suma
|
s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
|
s_sign <= not(s_dpc_uca(2)) and s_dpc_uca(1);
|
--! Instanciar el bloque de memorias MEMBLOCK
|
--! Instanciar el bloque de memorias MEMBLOCK
|
s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
|
s_resultfifo_wr <= s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(4)&s_resultsfifo_w(3)&s_resultsfifo_w(2)&s_resultsfifo_w(1)&s_resultsfifo_w(2)&s_resultsfifo_w(0);
|
s_int_rd_add <= s_addb&s_adda;
|
s_int_rd_add <= s_addb&s_adda;
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
MemoryBlock : memblock
|
MemoryBlock : memblock
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
dpfifo_rd => s_dpfifo_r,
|
dpfifo_rd => s_dpfifo_r,
|
normfifo_rd => s_normfifo_r,
|
normfifo_rd => s_normfifo_r,
|
dpfifo_wr => s_dpfifo_w,
|
dpfifo_wr => s_dpfifo_w,
|
normfifo_wr => s_normfifo_w,
|
normfifo_wr => s_normfifo_w,
|
instrfifo_rd => s_iq_rd_ack,
|
instrfifo_rd => s_iq_rd_ack,
|
resultfifo_wr => s_resultfifo_wr,
|
resultfifo_wr => s_resultfifo_wr,
|
instrfifo_empty => s_iq_empty,
|
instrfifo_empty => s_iq_empty,
|
ext_rd => rd,
|
ext_rd => rd,
|
ext_wr => wr,
|
ext_wr => wr,
|
ext_wr_add => add,
|
ext_wr_add => add,
|
ext_rd_add => add(12 downto 9),
|
ext_rd_add => add(12 downto 9),
|
ext_d => d,
|
ext_d => d,
|
resultfifo_full => s_rfull_events,
|
resultfifo_full => s_rfull_events,
|
int_d => s_results_d,
|
int_d => s_results_d,
|
status_register => s_eoi_events,
|
status_register => s_eoi_events,
|
ext_q => q,
|
ext_q => q,
|
instrfifo_q => s_iq,
|
instrfifo_q => s_iq,
|
int_q => s_q,
|
int_q => s_q,
|
int_rd_add => s_int_rd_add,
|
int_rd_add => s_int_rd_add,
|
dpfifo_d => s_dpfifo_d,
|
dpfifo_d => s_dpfifo_d,
|
normfifo_d => s_normfifo_d,
|
normfifo_d => s_normfifo_d,
|
dpfifo_q => s_dpfifo_q,
|
dpfifo_q => s_dpfifo_q,
|
normfifo_q => s_normfifo_q
|
normfifo_q => s_normfifo_q
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
--! Instanciar el bloque DPC
|
--! Instanciar el bloque DPC
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
DataPathControl_And_Syncronization_Block: dpc
|
DataPathControl_And_Syncronization_Block: dpc
|
port map (
|
port map (
|
|
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
paraminput => s_q,
|
paraminput => s_q,
|
prd32blko => s_p,
|
prd32blko => s_p,
|
add32blko => s_s,
|
add32blko => s_s,
|
sqr32blko => s_sq32,
|
sqr32blko => s_sq32,
|
inv32blko => s_qout32,
|
inv32blko => s_qout32,
|
fifo32x23_q => s_normfifo_q,
|
fifo32x23_q => s_normfifo_q,
|
fifo32x09_q => s_dpfifo_q,
|
fifo32x09_q => s_dpfifo_q,
|
unary => s_dpc_uca(2),
|
unary => s_dpc_uca(2),
|
crossprod => s_dpc_uca(1),
|
crossprod => s_dpc_uca(1),
|
addsub => s_dpc_uca(0),
|
addsub => s_dpc_uca(0),
|
sync_chain_0 => s_sync_chain_0,
|
sync_chain_0 => s_sync_chain_0,
|
eoi_int => s_eoi,
|
eoi_int => s_eoi,
|
eoi_demuxed_int => s_eoi_events,
|
eoi_demuxed_int => s_eoi_events,
|
sqr32blki => s_rd32,
|
sqr32blki => s_rd32,
|
inv32blki => s_dvd32,
|
inv32blki => s_dvd32,
|
fifo32x26_d => s_normfifo_d,
|
fifo32x26_d => s_normfifo_d,
|
fifo32x09_d => s_dpfifo_d,
|
fifo32x09_d => s_dpfifo_d,
|
prd32blki => s_f,
|
prd32blki => s_f,
|
add32blki => s_a,
|
add32blki => s_a,
|
resw => s_resultsfifo_w,
|
resw => s_resultsfifo_w,
|
fifo32x09_w => s_dpfifo_w,
|
fifo32x09_w => s_dpfifo_w,
|
fifo32x23_w => s_normfifo_w,
|
fifo32x23_w => s_normfifo_w,
|
fifo32x09_r => s_dpfifo_r,
|
fifo32x09_r => s_dpfifo_r,
|
fifo32x23_r => s_normfifo_r,
|
fifo32x23_r => s_normfifo_r,
|
resf_vector => s_rfull_events,
|
resf_vector => s_rfull_events,
|
resf_event => s_full_r,
|
resf_event => s_full_r,
|
resultoutput => s_results_d
|
resultoutput => s_results_d
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
|
|
--! Instanciar el bloque de inversion
|
--! Instanciar el bloque de inversion
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
inversion_block : invr32
|
inversion_block : invr32
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
dvd32 => s_dvd32,
|
dvd32 => s_dvd32,
|
qout32 => s_qout32
|
qout32 => s_qout32
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
--! Instanciar el bloque de raíz cuadrada.
|
--! Instanciar el bloque de raíz cuadrada.
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
square_root : sqrt32
|
square_root : sqrt32
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rd32 => s_rd32,
|
rd32 => s_rd32,
|
sq32 => s_sq32
|
sq32 => s_sq32
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
--! Instanciar el bloque aritmético.
|
--! Instanciar el bloque aritmético.
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
arithmetic_block : arithblock
|
arithmetic_block : arithblock
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
dpc => s_sign,
|
dpc => s_sign,
|
f => s_f,
|
f => s_f,
|
a => s_a,
|
a => s_a,
|
s => s_s,
|
s => s_s,
|
p => s_p
|
p => s_p
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
--! Instanciar la maquina de interrupciones
|
--! Instanciar la maquina de interrupciones
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
interruption_machine : im
|
interruption_machine : im
|
generic map (
|
generic map (
|
num_events => 4,
|
num_events => 4,
|
cycles_to_wait => 1023
|
cycles_to_wait => 1023
|
)
|
)
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
rfull_event => s_full_r,
|
rfull_event => s_full_r,
|
eoi_event => s_eoi,
|
eoi_event => s_eoi,
|
int => s_int,
|
int => s_int,
|
state => s_iCtrlState
|
state => s_iCtrlState
|
|
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
--!Instanciar la maquina de estados
|
--!Instanciar la maquina de estados
|
|
|
--!TBXINSTANCESTART
|
--!TBXINSTANCESTART
|
state_machine : sm
|
state_machine : sm
|
|
|
port map (
|
port map (
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
instrQq => s_iq,
|
instrQq => s_iq,
|
instrQ_empty => s_iq_empty,
|
instrQ_empty => s_iq_empty,
|
adda => s_adda,
|
adda => s_adda,
|
addb => s_addb,
|
addb => s_addb,
|
sync_chain_0 => s_sync_chain_0,
|
sync_chain_0 => s_sync_chain_0,
|
instrRdAckd => s_iq_rd_ack,
|
instrRdAckd => s_iq_rd_ack,
|
full_r => s_full_r,
|
full_r => s_full_r,
|
eoi => s_eoi,
|
eoi => s_eoi,
|
dpc_uca => s_dpc_uca,
|
dpc_uca => s_dpc_uca,
|
state => s_smState
|
state => s_smState
|
|
|
);
|
);
|
--!TBXINSTANCEEND
|
--!TBXINSTANCEEND
|
|
|
end architecture;
|
end architecture;
|
|
|
