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entity sm is
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entity sm is
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generic (
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generic (
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width : integer := 32;
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width : integer := 32;
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widthadmemblock : integer := 9
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widthadmemblock : integer := 9
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--!external_readable_widthad :
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--!external_readable_widthad :
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)
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);
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port (
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port (
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--! Señales normales de secuencia.
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clk,rst:in std_logic;
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clk,rst:in std_logic;
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adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
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--! ENTRADAS DE CONTROL DE SINCRONIZACION.
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sync_chain_d:out std_logic;
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--! Señales de sincronización de recursos.
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--! Las siguientes entradas tienen relevancia y son sensibles en los estados EXECUTE_INSTRUCTION y VERMEER_EXECUTE.
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--! ENTRADAS
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--! Instruction Q, instruction.
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--! Instruction Q, instruction.
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instrQq:in std_logic_vector(width-1 downto 0);
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instrQq:in std_logic_vector(width-1 downto 0);
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instrQ_empty:in std_logic;
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adda,addb:out std_logic_vector (widthadmemblock-1 downto 0);
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sync_chain_0,instrRdAckd:out std_logic;
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full_r: in std_logic; --! Indica que la cola de resultados no puede aceptar mas de 32 elementos.
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--! apempty, arithmetical pipeline empty.
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arithPbusy, instrQempty ,resultQfull: in std_logic;
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--! DataPath Control uca code.
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--! DataPath Control uca code.
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dpc_uca : out std_logic_vector (2 downto 0);
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dpc_uca : out std_logic_vector (2 downto 0)
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);
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);
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end entity;
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end entity;
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architecture sm_arch of sm is
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architecture sm_arch of sm is
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type macState is (FLUSH_TO_NEXT_INSTRUCTION,EXECUTE_INSTRUCTION);
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type macState is (LOAD_INSTRUCTION,FLUSH_ARITH_PIPELINE,EXECUTE_INSTRUCTION);
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--! LOAD_INSTRUCTION: Estado en el que se espera que en la cola de instrucciones haya una instrucción para ejecutar.
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--! EXECUTE_INSTRUCTION: Estado en el que se ejecuta la instrucción de la cola de instrucciones.
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--! FLUSH_ARITH_PIPELINE: Estado en el que se espera un número específico de ciclos de reloj, para que se desocupe el pipeline aritmético.
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signal state : macState;
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signal state : macState;
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constant rstMasterValue : std_logic:='0';
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constant rstMasterValue : std_logic:='0';
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component customCounter
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component customCounter
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generic (
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generic (
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EOBFLAG : string ;
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ZEROFLAG : string ;
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BACKWARDS : string ;
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EQUALFLAG : string ;
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subwidth : integer;
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width : integer
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width : integer
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);
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);
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port (
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port (
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clk,rst,go,set : in std_logic;
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clk,rst,go,set : in std_logic;
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setValue : in std_Logic_vector(width-1 downto 0);
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setValue,cmpBlockValue : in std_Logic_vector(width-1 downto subwidth);
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zero_flag,eob_flag,eq_flag : out std_logic;
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count : out std_logic_vector(width-1 downto 0)
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count : out std_logic_vector(width-1 downto 0)
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)
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);
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end component;
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signal addt0_blocka,addt0_blockb,set_Value_A,set_Value_B : std_logic_vector(widthadmemblock-1 downto 0);
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signal add_condition_a, add_condition_b,set_a,set_b : std_logic;
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signal s_dpc_uca, s_instrQ_uca : std_logic_vector(2 downto 0);
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signal s_block_start_a, s_block_start_b, s_block_end_a, s_block_end_b : std_logic_vector(4 downto 0);
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signal s_instr_uca: std_logic_vector(2 downto 0);
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signal s_dpc_uca: std_logic_vector(2 downto 0);
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signal s_block_start_a: std_logic_vector(4 downto 0);
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signal s_block_start_b: std_logic_vector(4 downto 0);
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signal s_block_end_a: std_logic_vector(4 downto 0);
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signal s_block_end_b: std_logic_vector(4 downto 0);
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signal s_combinatory: std_logic;
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signal s_delay_field: std_logic_vector(7 downto 0);
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signal s_set_b: std_logic; --! Señal para colocar un valor arbitrario en el contador B.
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signal s_set_a: std_logic;
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signal s_set_dly: std_logic;
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signal s_go_b: std_logic; --! Salida para controlar la pausa(0) o marcha(1) del contador de direcciones del operando B/D.
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signal s_go_a: std_logic; --! Salida para controlar la pausa(0) o marcha(1) del contador de direcciones del operando A/C.
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signal s_go_delay: std_logic; --! Salida para controlar la pausa(0) o marcha(1) del contador de delay, para el flush del pipeline aritmético.
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signal s_zeroFlag_delay:std_logic; --! Bandera de cero del contador delay.
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signal s_eq_b,s_eq_a: std_logic; --! Indica cuando se está leyendo el último bloque de memoria con operandos de entrada de a y de b respectivamente.
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signal s_eb_b,s_eb_a: std_logic; --! Indica que se está leyendo en memoria el último operando del bloque actual, b o a, respectivamente.
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begin
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begin
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--! Código UCA, pero en la etapa DPC: La diferencia es que UCA en la etapa DPC, decodifica el datapath dentro del pipeline aritmético.
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dpc_uca <= s_dpc_uca;
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--! Bloques asignados
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--! Bloques asignados en la instrucci´øn
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s_block_start_a <= instrQq(width-4 downto width-8);
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s_block_start_a <= instrQq(width-4 downto width-8);
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s_block_start_b <= instrQq(width-14 downto width-18);
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s_block_end_a <= instrQq(width-9 downto width-13);
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s_block_end_a <= instrQq(width-9 downto width-13);
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s_block_end_b <= instrQq(width-19 downto width-)
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s_block_start_b <= instrQq(width-14 downto width-18);
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s_block_end_b <= instrQq(width-19 downto width-23);
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--! Campo que define si la instrucción es combinatoria
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s_combinatory <= instrQq(width-24);
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--! Campo que define cuantos clocks debe esperar el sistema, despues de que se ejecuta una instrucción, para que el pipeline aritmético quede vacio.
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s_delay_field <= instrQq(width-25 downto width-32);
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--! UCA code, código con la instrucción a ejecutar.
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s_instr_uca <= instrQq(31 downto 29);
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--! Address Counters
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--! Address Counters
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counterA:customCounter
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counterA:customCounter
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port map (clk,rst,add_condition_a,set_a,instrQq(width-4 downto width-8)&x"0",addt0_blocka);
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generic map ("YES","NO","NO","YES",4,9)
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port map (clk,rst,s_go_a,s_set_a,s_block_start_a,s_block_end_a,open,s_eb_a,s_eq_a,adda);
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counterB:customCounter
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counterB:customCounter
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port map (clk,rst,add_condition_b,set_b,instrQq(width-9 downto width-12)&x"0",addt0_blockb);
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generic map ("YES","NO","NO","YES",4,9)
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adda <= addt0_blocka;
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port map (clk,rst,s_go_b,s_set_b,s_block_start_b,s_block_end_b,open,s_eb_b,s_eq_b,addb);
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addb <= addt0_blockb;
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counterDly:customCounter
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generic map("NO","YES","YES","NO",0,5)
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port map (clk,rst,s_go_delay,s_set_dly,s_delay_field(4 downto 0),"00000",s_zeroFlag_delay,open,open,open);
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--! uca code
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s_instrQ_uca <= instrQq(31 downto 29);
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sm_comb:
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process (state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
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begin
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--!Señal de play/pause del contador de direcciones para el parámetro B/D.
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s_go_b <= not(full_r and s_eb_b);
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--!Señal de play/pause del contador de direcciones para el parámetro A/C.
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if s_combinatory='0' then
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s_go_a <= not(full_r and s_eb_b);
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else
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s_go_a <= not(full_r) and s_eb_b and s_eq_b;
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end if;
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--!Señal de play/pause del contador del arithmetic pipeline flush counter.
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s_go_delay <= not(s_zeroFlag_delay);
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--! Si estamos en el final de la instrucción, "descargamos" esta de la máquina de estados con acknowledge read.
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if s_eb_b='1' and s_eq_b='1' and s_eb_a='1' and s_eq_a='1' and state=EXECUTE_INSTRUCTION then
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instrRdAckd <= '1';
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else
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instrRdAckd <= '0';
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end if;
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if (s_eb_a='1' and s_eq_a='1') or state=LOAD_INSTRUCTION or state=FLUSH_ARITH_PIPELINE then
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s_set_a <= '1';
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else
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s_set_a <= '0';
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end if;
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if (s_eb_b='1' and s_eq_b='1') or state=LOAD_INSTRUCTION or state=FLUSH_ARITH_PIPELINE then
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s_set_b <= '1';
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else
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s_set_b <= '0';
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end if;
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end process;
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sm_proc:
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sm_proc:
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process (clk,rst)
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process (clk,rst,state, full_r,s_eb_b,s_combinatory,s_zeroFlag_delay,s_eq_b,s_eb_a,s_eq_a,instrQ_empty)
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begin
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begin
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if rst=rstMasterValue then
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if rst=rstMasterValue then
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state <= IDLE;
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ird_ack <= '0';
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state <= LOAD_INSTRUCTION;
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s_set_dly <= '1';
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sync_chain_0 <= '0';
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s_dpc_uca <= (others => '0');
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elsif clk='1' and clk'event then
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elsif clk='1' and clk'event then
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case state is
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case state is
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when FLUSH_TO_NEXT_INSTRUCTION =>
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--! Chequear si hay una instruccion en la salida de la cola de instruccioens.
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--! Cargar la siguiente instrucción.
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if instrQempty='0' then
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when LOAD_INSTRUCTION =>
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if instrQ_empty='0' and full_r='0' then
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--! Siguiente estado: Ejecutar la instrucción.
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state <= EXECUTE_INSTRUCTION;
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--! Chequear si la cola de resultados tiene espacio.
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--! Asignar el código UCA para que comience la decodificación.
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if resultQfull='0' then
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s_dpc_uca <= s_instr_uca;
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--! Si el codigo de instruccion (uca) que se encuentra en el DPC es igual al que se encuentra en la instruccion de la salida de la cola de instrucciones, entonces no hay mas validaciones que hacer.
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--! Validar el siguiente dato dentro del pipeline aritmético.
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sync_chain_0 <= '1';
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--! En el estado EXECUTE, el valor del contador de delay se debe mantener fijo, y puesto en el valor de delay que contiene la instruccion.
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s_set_dly <= '1';
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--! Now check that arithmetic pipline is not busy
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if arithPbusy='0' then
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end if;
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--! Ejecución de la instruccion
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when EXECUTE_INSTRUCTION =>
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when EXECUTE_INSTRUCTION =>
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if addt1_blockb(4 downto 0)=x"1f" and addt1_blocka=x"1f" then
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if addt1_blockb(8 downto )
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if s_eb_b='1'and s_eq_b='1' and s_eb_a='1' and s_eq_a='1' then --! Revisar si es el fin de la instruccion
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--!Ya no ingresaran mas datos al pipeline aritmético, invalidar.
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sync_chain_0 <= '0';
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if s_zeroFlag_delay='1' then
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state <= LOAD_INSTRUCTION;
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s_set_dly <= '1';
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else
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state <= FLUSH_ARITH_PIPELINE;
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s_set_dly <= '0';
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end if;
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--! Invalidar/validar datos dentro del pipeline aritmético.
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elsif s_eb_b='1' and full_r='1' then
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--! Invalidar el siguiente dato dentro del pipeline aritmético.
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sync_chain_0 <= '0';
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else
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else
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sync_chain_0 <= '1';
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end if;
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--! Ejecución de la instrucción
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when FLUSH_ARITH_PIPELINE =>
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--! Este estado permanece así hasta que, haya una instrucción
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if s_zeroFlag_delay='1' then
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state <= LOAD_INSTRUCTION;
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s_set_dly <= '1';
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end if;
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end if;
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when others => null;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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nxtadda_proc:
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process ()
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end architecture;
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end architecture;
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No newline at end of file
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