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--! @file ap_n_dpc.vhd
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--! @brief Decodificador de operacién. Sistema de decodificación de los \kdatapaths, cuyo objetivo es a partir del par´ametro de entrada DCS.\nSon 4 las posibles configuraciones de \kdatapaths que existen. Los valores de los bits DC son los que determinan y decodifican la interconexión entre los componentes aritméticos. El componente S determina el signo de la operación cuando es una suma la que operación se eséa; ejecutando en el momento.
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--! @author Julián Andrés Guarín Reyes
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--------------------------------------------------------------
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-- RAYTRAC
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-- Author Julian Andres Guarin
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-- ap_n_dpc.vhd
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-- This file is part of raytrac.
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--
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-- raytrac is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- raytrac is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with raytrac. If not, see <http://www.gnu.org/licenses/>.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use work.arithpack.all;
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library altera_mf;
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use altera_mf.altera_mf_components.all;
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entity ap_n_dpc is
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port (
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clk : in std_logic;
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rst : in std_logic;
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paraminput : in vectorblock06; --! Vectores A,B
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d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
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sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
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sync_chain_pending : out std_logic; --! Señal para indicar si hay datos en el pipeline aritmético.
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qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
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qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
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);
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end entity;
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architecture ap_n_dpc_arch of ap_n_dpc is
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--!TBXSTART:FACTORS_N_ADDENDS
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signal sfactor : vectorblock12;
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signal ssumando : vectorblock06;
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signal sdpfifo_q : xfloat32;
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--!TBXEND
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--!TBXSTART:ARITHMETIC_RESULTS
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signal sresult : vectorblock04;
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signal sprd32blk : vectorblock06;
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signal sadd32blk : vectorblock03;
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signal ssqr32blk : xfloat32;
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signal sinv32blk : xfloat32;
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signal sqxyz_q : vectorblock03;
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signal sqxyz_e : std_logic;
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--!TBXEND
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--!TBXSTART:SYNC_CHAIN
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signal ssync_chain : std_logic_vector(25 downto 2);
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--!TBXEND
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signal qxyzd : std_logic_vector(95 downto 0);
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signal qxyzq : std_logic_vector(95 downto 0);
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signal sq1_d : std_logic_vector(31 downto 0);
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signal sq1_q : std_logic_vector(31 downto 0);
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signal sq1_w : std_logic;
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signal sq1_e : std_logic;
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signal sadd32blko : vectorblock03; --! Salidas de los 3 sumadores.
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signal sprd32blko : vectorblock06; --! Salidas de los 6 multiplicadores.
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signal sinv32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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signal ssqr32blko : xfloat32; --! Salidas de la raiz cuadradas y el inversor.
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--! Bloque Aritmetico de Sumadores y Multiplicadores (madd)
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component arithblock
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port (
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clk : in std_logic;
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rst : in std_logic;
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sign : in std_logic;
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prd32blki : in vectorblock12;
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add32blki : in vectorblock06;
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add32blko : out vectorblock03;
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prd32blko : out vectorblock06;
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sq32o : out xfloat32;
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inv32o : out xfloat32
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);
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end component;
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begin
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--! Bloque Aritmético
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ap : arithblock
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port map (
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clk => clk,
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rst => rst,
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sign => s,
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prd32blki => sfactor,
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add32blki => ssumando,
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add32blko => sadd32blko,
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prd32blko => sprd32blko,
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sq32o => ssqr32blko,
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inv32o => sinv32blko
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);
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--! Cadena de sincronización: 29 posiciones.
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sync_chain_pending <= sync_chain_1 or not(sq1_e) or not(sqxyz_e);
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sync_chain_proc:
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process(clk,rst,sync_chain_1)
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begin
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if rst=rstMasterValue then
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ssync_chain(25 downto 2) <= (others => '0');
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elsif clk'event and clk='1' then
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for i in 25 downto 3 loop
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ssync_chain(i) <= ssync_chain(i-1);
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end loop;
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ssync_chain(2) <= sync_chain_1;
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end if;
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end process sync_chain_proc;
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--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, simplemente son abstracciones a nivel de código y no representará cambios en la síntesis.
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qresult_d <= sresult;
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--! El siguiente código sirve para conectar arreglos a señales std_logic_1164, son abstracciones de código también, sin embargo se realizan a través de registros.
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register_products_outputs:
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process (clk)
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begin
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if clk'event and clk='1' then
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sprd32blk <= sprd32blko;
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sadd32blk <= sadd32blko;
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sinv32blk <= sinv32blko;
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--! Raiz Cuadrada.
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ssqr32blk <= ssqr32blko;
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end if;
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end process;
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--! Decodificación del Datapath.
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datapathproc:process(s,d,c,paraminput,sinv32blk,sprd32blk,sadd32blk,sdpfifo_q,sqxyz_q,ssync_chain,ssqr32blk,sq1_q)
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begin
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--Summador 0: DORC!
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if (d or c)='1' then
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ssumando(s0) <= sprd32blk(p0);
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ssumando(s1) <= sprd32blk(p1);
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else
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ssumando(s0) <= paraminput(ax);
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ssumando(s1) <= paraminput(bx);
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end if;
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--Sumador 1:
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if d='1' then
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ssumando(s2) <= sadd32blk(a0);
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ssumando(s3) <= sdpfifo_q;
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elsif c='0' then
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ssumando(s2) <= paraminput(ay);
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ssumando(s3) <= paraminput(by);
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else
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ssumando(s2) <= sprd32blk(p2);
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ssumando(s3) <= sprd32blk(p3);
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end if;
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--S2
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if c='0' then
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ssumando(s4) <= paraminput(az);
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ssumando(s5) <= paraminput(bz);
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else
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ssumando(s4) <= sprd32blk(p4);
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ssumando(s5) <= sprd32blk(p5);
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end if;
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--P0,P1,P2
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sfactor(f4) <= paraminput(az);
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if (not(d) and c)='1' then
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sfactor(f0) <= paraminput(ay);
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sfactor(f1) <= paraminput(bz);
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sfactor(f2) <= paraminput(az);
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sfactor(f3) <= paraminput(by);
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sfactor(f5) <= paraminput(bx);
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else
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sfactor(f0) <= paraminput(ax);
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sfactor(f2) <= paraminput(ay);
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sfactor(f1) <= paraminput(bx) ;
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sfactor(f3) <= paraminput(by) ;
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sfactor(f5) <= paraminput(bz) ;
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end if;
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--P3 P4 P5
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if (c and s)='1' then
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sfactor(f6) <= paraminput(ax);
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sfactor(f9) <= paraminput(by);
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else
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sfactor(f6) <= sinv32blk;
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sfactor(f9) <= sqxyz_q(qy);
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end if;
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if d='1' then
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if s='0' then
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sfactor(f7) <= sqxyz_q(qx);
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sfactor(f8) <= sinv32blk;
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sfactor(f10) <= sinv32blk;
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sfactor(f11) <= sqxyz_q(qz);
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else
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sfactor(f7) <= paraminput(bx);
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sfactor(f8) <= paraminput(ay);
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sfactor(f10) <= paraminput(az);
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sfactor(f11) <= paraminput(bz);
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end if;
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else
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sfactor(f7) <= paraminput(bz);
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sfactor(f8) <= paraminput(ax);
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sfactor(f10) <= paraminput(ay);
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sfactor(f11) <= paraminput(bx);
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end if;
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--res0,1,2
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if d='1' then
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sresult(qx) <= sprd32blk(p3);
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sresult(qy) <= sprd32blk(p4);
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sresult(qz) <= sprd32blk(p5);
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else
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sresult(qx) <= sadd32blk(a0);
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sresult(qy) <= sadd32blk(a1);
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sresult(qz) <= sadd32blk(a2);
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end if;
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--res3
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sresult(qsc) <= sq1_q;
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if c='1' then
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sq1_d <= ssqr32blk;
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sq1_w <= ssync_chain(20) and d;
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else
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sq1_w <= ssync_chain(19) and d;
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sq1_d <= sadd32blk(a1);
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end if;
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if d='1' then
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if s='1'then
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qresult_w <= ssync_chain(5);
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else
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qresult_w<= ssync_chain(25);
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end if;
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else
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if c='1' and s='1' then
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qresult_w <= ssync_chain(12);
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elsif c='0' then
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qresult_w <= ssync_chain(8);
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else
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qresult_w <= '0';
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end if;
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end if;
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end process;
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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q0 : scfifo --! Debe ir registrada la salida.
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generic map (
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allow_rwcycle_when_full => "ON",
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lpm_widthu => 3,
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lpm_numwords => 6,
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lpm_showahead => "ON",
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lpm_width => 32,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "OFF"
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)
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port map (
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sclr => '0',
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clock => clk,
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rdreq => ssync_chain(12),
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wrreq => ssync_chain(5),
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data => sprd32blk(p2),
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q => sdpfifo_q
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);
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--! Colas internas de producto punto, ubicada en el pipe line aritméco. Paralelo a los sumadores a0 y a2.
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q1 : scfifo --! Debe ir registrada la salida.
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generic map (
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allow_rwcycle_when_full => "ON",
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lpm_widthu => 3,
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lpm_numwords => 5,
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lpm_showahead => "ON",
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lpm_type => "SCIFIFO",
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lpm_width => 32,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "OFF"
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)
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port map (
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rdreq => ssync_chain(25),
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sclr => '0',
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clock => clk,
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empty => sq1_e,
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q => sq1_q,
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wrreq => sq1_w,
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data => sq1_d
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);
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--! Cola interna de normalización de vectores, ubicada entre el pipeline aritmético
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qxyzd(ax*32+31 downto ax*32) <= paraminput(ax);
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qxyzd(ay*32+31 downto ay*32) <= paraminput(ay);
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qxyzd(az*32+31 downto az*32) <= paraminput(az);
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sqxyz_q(ax) <= qxyzq(ax*32+31 downto ax*32);
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sqxyz_q(ay) <= qxyzq(ay*32+31 downto ay*32);
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sqxyz_q(az) <= qxyzq(az*32+31 downto az*32);
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qxqyqz : scfifo
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generic map (
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allow_rwcycle_when_full => "ON",
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lpm_widthu => 5,
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lpm_numwords => 32,
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lpm_showahead => "ON",
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lpm_width => 96,
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overflow_checking => "ON",
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underflow_checking => "ON",
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use_eab => "ON"
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)
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port map (
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aclr => '0',
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clock => clk,
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empty => sqxyz_e,
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rdreq => ssync_chain(21),
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wrreq => sync_chain_1,
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data => qxyzd,
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q => qxyzq
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);
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end architecture;
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