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[/] [raytrac/] [branches/] [fp_sgdma/] [ap_n_dpc.vhd] - Diff between revs 242 and 248

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Rev 242 Rev 248
Line 31... Line 31...
 
 
entity ap_n_dpc is
entity ap_n_dpc is
 
 
        port (
        port (
 
 
                p0,p1,p2                                        : out std_logic_vector(31 downto 0);
                p0,p1,p2,p3,p4,p5,p6,p7,p8: out std_logic_vector(31 downto 0);
 
 
 
 
                clk                                             : in    std_logic;
                clk                                             : in    std_logic;
                rst                                             : in    std_logic;
                rst                                             : in    std_logic;
 
 
Line 68... Line 68...
        );
        );
end entity;
end entity;
 
 
architecture ap_n_dpc_arch of ap_n_dpc is
architecture ap_n_dpc_arch of ap_n_dpc is
        --!Constantes de apoyo
        --!Constantes de apoyo
        constant ssync_chain_max : integer :=27;
        constant ssync_chain_max : integer :=32;
        constant ssync_chain_min : integer :=2;
        constant ssync_chain_min : integer :=2;
 
 
        --! Tunnning delay
        --! Tunnning delay
        constant adder2_delay: integer := 1;
        constant adder2_delay: integer := 1;
        constant adder1_delay : integer := 1;
        constant adder1_delay : integer := 1;
Line 287... Line 287...
                                ssync_chain(i) <= ssync_chain(i-1);
                                ssync_chain(i) <= ssync_chain(i-1);
                        end loop;
                        end loop;
                        ssync_chain(ssync_chain_min) <= sync_chain_1;
                        ssync_chain(ssync_chain_min) <= sync_chain_1;
 
 
                        --! Salida de los multiplicadores p0 p1 p2 
                        --! Salida de los multiplicadores p0 p1 p2 
                        if ssync_chain(21)='1' then
                        if ssync_chain(23)='1' then
                                p0 <= sa0; -- El resultado quedara consignado en VZ1=BASE+1
                                p0 <= ssq32; -- El resultado quedara consignado en VZ1=BASE+1
                        elsif ssync_chain(22)='1' then
                        elsif ssync_chain(28)='1' then
                                p1 <= sa0; -- El resutlado quedara consignado en VY1=BASE+2
                                p1 <= sq2_q; -- El resultado quedara consignado en VX1=BASE+3
                        elsif ssync_chain(23)='1' then
                        elsif ssync_chain(24)='1' then
                                p2 <= sa0; -- El resultado quedara consignado en VX1=BASE+3
                                p2 <= sinv32; -- El resutlado quedara consignado en VY1=BASE+2
 
                                p3 <= sqx_q;
 
                                p4 <= sqy_q;
 
                                p5 <= sqz_q;
 
                        elsif ssync_chain(28)='1' then
 
                                p6 <= sp3o;
 
                                p7 <= sp4o;
 
                                p8 <= sp5o;
                        end if;
                        end if;
 
 
                end if;
                end if;
        end process sync_chain_proc;
        end process sync_chain_proc;
 
 
Line 427... Line 434...
 
 
                                sqr_dx <= sp3;
                                sqr_dx <= sp3;
                                sqr_dy <= sp4;
                                sqr_dy <= sp4;
                                sqr_dz <= sp5;
                                sqr_dz <= sp5;
 
 
                                sqr_w <= ssync_chain(27);
                                sqr_w <= ssync_chain(27+adder1_delay);
 
 
                        when others =>
                        when others =>
 
 
                                sq2_w <= '0';
                                sq2_w <= '0';
                                sq2_d <= ssq32;
                                sq2_d <= ssq32;
Line 502... Line 509...
                overflow_checking               => "ON",
                overflow_checking               => "ON",
                underflow_checking              => "ON",
                underflow_checking              => "ON",
                use_eab                                 => "ON"
                use_eab                                 => "ON"
        )
        )
        port map (
        port map (
                rdreq           => ssync_chain(27),
                rdreq           => ssync_chain(28),
                sclr            => '0',
                sclr            => '0',
                clock           => clk,
                clock           => clk,
                empty           => sq2_e,
                empty           => sq2_e,
                q                       => sqr_dsc,
                q                       => sqr_dsc,
                wrreq           => sq2_w,
                wrreq           => sq2_w,
Line 527... Line 534...
        )
        )
        port    map (
        port    map (
                aclr            => '0',
                aclr            => '0',
                clock           => clk,
                clock           => clk,
                empty           => sq1_e,
                empty           => sq1_e,
                rdreq           => ssync_chain(23),
                rdreq           => ssync_chain(23+adder1_delay),
                wrreq           => sync_chain_1,
                wrreq           => sync_chain_1,
                data            => ax,
                data            => ax,
                q                       => sqx_q
                q                       => sqx_q
        );
        );
        qy : scfifo
        qy : scfifo
Line 546... Line 553...
                use_eab                                 => "ON"
                use_eab                                 => "ON"
        )
        )
        port    map (
        port    map (
                aclr            => '0',
                aclr            => '0',
                clock           => clk,
                clock           => clk,
                rdreq           => ssync_chain(23),
                rdreq           => ssync_chain(23+adder1_delay),
                wrreq           => sync_chain_1,
                wrreq           => sync_chain_1,
                data            => ay,
                data            => ay,
                q                       => sqy_q
                q                       => sqy_q
        );
        );
        qz : scfifo
        qz : scfifo
Line 565... Line 572...
                use_eab                                 => "ON"
                use_eab                                 => "ON"
        )
        )
        port    map (
        port    map (
                aclr            => '0',
                aclr            => '0',
                clock           => clk,
                clock           => clk,
                rdreq           => ssync_chain(23),
                rdreq           => ssync_chain(23+adder1_delay),
                wrreq           => sync_chain_1,
                wrreq           => sync_chain_1,
                data            => az,
                data            => az,
                q                       => sqz_q
                q                       => sqz_q
        );
        );
--!***********************************************************************************************************
--!***********************************************************************************************************

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