Line 72... |
Line 72... |
end entity;
|
end entity;
|
|
|
|
|
architecture raytrac_arch of raytrac is
|
architecture raytrac_arch of raytrac is
|
|
|
|
--! Debug
|
|
signal ssumando5 : xfloat32;
|
|
signal sphantom_q: std_logic_vector(31 downto 0);
|
|
|
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
|
--! Altera Compiler Directive, to avoid m9k autoinferring thanks to the guys at http://www.alteraforum.com/forum/archive/index.php/t-30784.html ....
|
attribute altera_attribute : string;
|
--attribute altera_attribute : string;
|
attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
|
--attribute altera_attribute of raytrac_arch : architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
|
|
|
|
|
type registerblock is array (15 downto 0) of xfloat32;
|
type registerblock is array (15 downto 0) of xfloat32;
|
type transferState is (IDLE,SINK,SOURCE);
|
type transferState is (IDLE,SINK,SOURCE);
|
type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
|
type upload_chain is (UPVX,UPVY,UPVZ,SC,DMA);
|
Line 121... |
Line 125... |
constant reg_ctrl_flags_dp : integer:=12; --! Data Pending flag.
|
constant reg_ctrl_flags_dp : integer:=12; --! Data Pending flag.
|
constant reg_ctrl_flags_ap : integer:=13; --! Address Pending Flag.
|
constant reg_ctrl_flags_ap : integer:=13; --! Address Pending Flag.
|
constant reg_ctrl_rlsc : integer:=14; --! RLSC bit : Reload Load Sync Chain.
|
constant reg_ctrl_rlsc : integer:=14; --! RLSC bit : Reload Load Sync Chain.
|
constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
|
constant reg_ctrl_rom : integer:=15; --! ROM bit : Read Only Mode bit.
|
|
|
constant reg_ctrl_nfetch_low : integer:=16; --! NFETCH_LOW : Lower bit to program the number of addresses to load in the interconnection.
|
constant reg_ctrl_alb : integer:=16; --! Conditional Writing. A<B.
|
|
constant reg_ctrl_aeb : integer:=17; --! A==B.
|
|
constant reg_ctrl_ageb : integer:=18; --! A>=B.
|
|
constant reg_ctrl_nfetch_low : integer:=19; --! NFETCH_LOW : Lower bit to program the number of addresses to load in the interconnection.
|
constant reg_ctrl_nfetch_high : integer:=30; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
|
constant reg_ctrl_nfetch_high : integer:=30; --! NFETCH_HIGH : Higher bit to program the number of addresses to load in the interconnection.
|
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
|
constant reg_ctrl_irq : integer:=31; --! IRQ bit : Interrupt Request Signal.
|
|
|
|
|
--! Avalon MM Slave
|
--! Avalon MM Slave
|
|
|
signal sreg_block : registerblock;
|
signal sreg_block : registerblock;
|
signal sslave_read : std_logic;
|
signal sslave_read : std_logic;
|
signal sslave_write : std_logic;
|
signal sslave_write : std_logic;
|
signal sslave_writedata : std_logic_vector (wd-1 downto 0);
|
signal sslave_writedata : std_logic_vector (wd-1 downto 0);
|
signal sslave_address : std_logic_vector (3 downto 0);
|
signal sslave_address : std_logic_vector (3 downto 0);
|
Line 141... |
Line 149... |
signal smaster_read : std_logic;
|
signal smaster_read : std_logic;
|
|
|
--! State Machine and event signaling
|
--! State Machine and event signaling
|
signal sm : transferState;
|
signal sm : transferState;
|
|
|
signal sres_ack : std_logic;
|
signal sr_e : std_logic;
|
|
signal sr_ack : std_logic;
|
signal soutb_ack : std_logic;
|
signal soutb_ack : std_logic;
|
|
|
signal sres_q : std_logic_vector (4*wd-1 downto 0);
|
|
|
|
signal sres_d : vectorblock04;
|
|
signal soutb_d : std_logic_vector(wd-1 downto 0);
|
signal soutb_d : std_logic_vector(wd-1 downto 0);
|
|
|
|
|
signal sres_w : std_logic;
|
|
signal soutb_w : std_logic;
|
signal soutb_w : std_logic;
|
|
|
signal sres_e : std_logic;
|
|
signal soutb_e : std_logic;
|
signal soutb_e : std_logic;
|
signal soutb_ae : std_logic;
|
signal soutb_ae : std_logic;
|
signal soutb_af : std_logic;
|
signal soutb_af : std_logic;
|
|
|
|
|
signal soutb_usedw : std_logic_vector(fd-1 downto 0);
|
signal soutb_usedw : std_logic_vector(fd-1 downto 0);
|
|
|
signal ssync_chain_1 : std_logic;
|
signal ssync_chain_1 : std_logic;
|
|
|
signal ssync_chain_pending : std_logic;
|
signal ssync_chain_pending : std_logic;
|
signal sfetch_data_pending : std_logic;
|
signal sfetch_data_pending : std_logic;
|
signal sload_add_pending : std_logic;
|
signal sload_add_pending : std_logic;
|
signal spipeline_pending : std_logic;
|
signal spipeline_pending : std_logic;
|
signal swrite_pending : std_logic;
|
signal swrite_pending : std_logic;
|
Line 194... |
Line 199... |
signal sflood_burstcount : std_logic_vector(mb downto 0);
|
signal sflood_burstcount : std_logic_vector(mb downto 0);
|
|
|
--! Arithmetic Pipeline and Data Path Control
|
--! Arithmetic Pipeline and Data Path Control
|
component ap_n_dpc
|
component ap_n_dpc
|
port (
|
port (
|
|
|
|
sumando5 : out xfloat32;
|
|
|
clk : in std_logic;
|
clk : in std_logic;
|
rst : in std_logic;
|
rst : in std_logic;
|
|
|
paraminput : in vectorblock06; --! Vectores A,B
|
dx : out std_logic_vector(31 downto 0);
|
|
dy : out std_logic_vector(31 downto 0);
|
|
dz : out std_logic_vector(31 downto 0);
|
|
dsc : out std_logic_vector(31 downto 0);
|
|
ax : in std_logic_vector(31 downto 0);
|
|
ay : in std_logic_vector(31 downto 0);
|
|
az : in std_logic_vector(31 downto 0);
|
|
bx : in std_logic_vector(31 downto 0);
|
|
by : in std_logic_vector(31 downto 0);
|
|
bz : in std_logic_vector(31 downto 0);
|
|
vx : out std_logic_vector(31 downto 0);
|
|
vy : out std_logic_vector(31 downto 0);
|
|
vz : out std_logic_vector(31 downto 0);
|
|
sc : out std_logic_vector(31 downto 0);
|
|
ack : in std_logic;
|
|
empty : out std_logic;
|
|
--paraminput : in vectorblock06; --! Vectores A,B
|
|
|
d,c,s : in std_logic; --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
|
dcs : in std_logic_vector(2 downto 0); --! Bit con el identificador del bloque AB vs CD e identificador del sub bloque (A/B) o (C/D).
|
|
|
sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
|
sync_chain_1 : in std_logic; --! Señal de dato valido que se va por toda la cadena de sincronizacion.
|
sync_chain_pending : out std_logic;
|
pipeline_pending : out std_logic --! Señal para indicar si hay datos en el pipeline aritmético.
|
|
|
|
|
qresult_w : out std_logic; --! Salidas de escritura y lectura en las colas de resultados.
|
|
qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
|
--qresult_d : out vectorblock04 --! 4 salidas de resultados, pues lo máximo que podrá calcularse por cada clock son 2 vectores.
|
|
|
);
|
);
|
end component;
|
end component;
|
|
|
signal sparaminput : vectorblock06;
|
signal svx,svy,svz,ssc : std_logic_vector(31 downto 0);
|
|
signal sdx,sdy,sdz,sdsc : std_logic_vector(31 downto 0);
|
|
|
begin
|
begin
|
|
|
--!Zero agreggate
|
--!Zero agreggate
|
zero <= (others => '0');
|
zero <= (others => '0');
|
|
|
sparaminput(ax) <= sreg_block(reg_ax);
|
|
sparaminput(ay) <= sreg_block(reg_ay);
|
|
sparaminput(az) <= sreg_block(reg_az);
|
|
sparaminput(bx) <= sreg_block(reg_bx);
|
|
sparaminput(by) <= sreg_block(reg_by);
|
|
sparaminput(bz) <= sreg_block(reg_bz);
|
|
|
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! ARITHMETIC PIPELINE AND DATA PATH INSTANTIATION => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
|
|
--! Arithpipeline and Datapath Control Instance
|
--! Arithpipeline and Datapath Control Instance
|
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
|
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
|
port map (
|
port map (
|
|
sumando5 => ssumando5,
|
|
|
clk => clk,
|
clk => clk,
|
rst => rst,
|
rst => rst,
|
paraminput => sparaminput,
|
dx => sdx,
|
d => sreg_block(reg_ctrl)(reg_ctrl_d),
|
dy => sdy,
|
c => sreg_block(reg_ctrl)(reg_ctrl_c),
|
dz => sdz,
|
s => sreg_block(reg_ctrl)(reg_ctrl_s),
|
dsc => sdsc,
|
|
ax => sreg_block(reg_ax),
|
|
ay => sreg_block(reg_ay),
|
|
az => sreg_block(reg_az),
|
|
bx => sreg_block(reg_bx),
|
|
by => sreg_block(reg_by),
|
|
bz => sreg_block(reg_bz),
|
|
vx => svx,
|
|
vy => svy,
|
|
vz => svz,
|
|
sc => ssc,
|
|
ack => sr_ack,
|
|
empty => sr_e,
|
|
dcs => sreg_block(reg_ctrl)(reg_ctrl_d downto reg_ctrl_s),
|
sync_chain_1 => ssync_chain_1,
|
sync_chain_1 => ssync_chain_1,
|
sync_chain_pending => ssync_chain_pending,
|
pipeline_pending => spipeline_pending
|
qresult_w => sres_w,
|
|
qresult_d => sres_d
|
|
|
|
|
|
);
|
);
|
|
|
|
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! TRANSFER CONTROL RTL CODE
|
--! TRANSFER CONTROL RTL CODE
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
TRANSFER_CONTROL:
|
TRANSFER_CONTROL:
|
process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,sres_e,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
|
process(clk,rst,master_waitrequest,sm,soutb_ae,soutb_usedw,spipeline_pending,soutb_e,zero,soutb_af,sfetch_data_pending,sreg_block,sslave_write,sslave_address,sslave_writedata,ssync_chain_pending,smaster_read,smaster_write,sdata_fetch_counter,sload_add_pending,swrite_pending,sdownload_chain)
|
begin
|
begin
|
|
|
--! Conexióln a señales externas.
|
--! Conexióln a señales externas.
|
irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
|
irq <= sreg_block(reg_ctrl)(reg_ctrl_irq);
|
master_read <= smaster_read;
|
master_read <= smaster_read;
|
Line 268... |
Line 299... |
sZeroTransit <= not(sload_add_pending or sfetch_data_pending or spipeline_pending or swrite_pending);
|
sZeroTransit <= not(sload_add_pending or sfetch_data_pending or spipeline_pending or swrite_pending);
|
|
|
--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
|
--! ELEMENTO DE SINCRONIZACION OUT QUEUE: Datos pendientes por cargar a la memoria a través de la interconexión
|
swrite_pending <= not(soutb_e);
|
swrite_pending <= not(soutb_e);
|
|
|
--! ELEMENTO DE SINCRONIZACION ARITH PIPELINE: Hay datos transitando por el pipeline aritmético.
|
|
if ssync_chain_pending='1' or sres_e='0' then
|
|
spipeline_pending <= '1';
|
|
else
|
|
spipeline_pending <= '0';
|
|
end if;
|
|
|
|
--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
|
--! ELEMENTO DE SINCRONIZACION DESCARGA DE DATOS: Hay datos pendientes por descargar desde la memoria a través de la interconexión.
|
if sdata_fetch_counter=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) then
|
if sdata_fetch_counter=zero(reg_ctrl_nfetch_high downto reg_ctrl_nfetch_low) then
|
sfetch_data_pending <= '0';
|
sfetch_data_pending <= '0';
|
else
|
else
|
Line 481... |
Line 506... |
when x"0" =>
|
when x"0" =>
|
--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
|
--! Solo se permitira escribir en el registro de control si no hay una interrupción activa o si la hay solamente si se esta intentando desactivar la interrupci´n
|
if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
|
if sreg_block(reg_ctrl)(reg_ctrl_irq)='0' or sslave_writedata(reg_ctrl_irq)='0' then
|
sreg_block(reg_ctrl)(reg_ctrl_irq downto reg_ctrl_nfetch_low) <= sslave_writedata(reg_ctrl_irq downto reg_ctrl_nfetch_low);
|
sreg_block(reg_ctrl)(reg_ctrl_irq downto reg_ctrl_nfetch_low) <= sslave_writedata(reg_ctrl_irq downto reg_ctrl_nfetch_low);
|
sreg_block(reg_ctrl)(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb) <= sslave_writedata(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb);
|
sreg_block(reg_ctrl)(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb) <= sslave_writedata(reg_ctrl_flags_wp-1 downto reg_ctrl_cmb);
|
|
sreg_block(reg_ctrl)(reg_ctrl_rlsc) <= sslave_writedata(reg_ctrl_rlsc);
|
|
sreg_block(reg_ctrl)(reg_ctrl_ageb downto reg_ctrl_alb) <=sslave_writedata(reg_ctrl_ageb downto reg_ctrl_alb);
|
end if;
|
end if;
|
when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
|
when x"6" => sreg_block(reg_outputcounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"7" => sreg_block(reg_inputcounter) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"8" => sreg_block(reg_fetchstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
when x"9" => sreg_block(reg_sinkstart) <= sslave_writedata;
|
Line 509... |
Line 536... |
end if;
|
end if;
|
end process;
|
end process;
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! FLOW CONTROL RTL CODE
|
--! FLOW CONTROL RTL CODE
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! Colas de resultados y buffer de salida
|
--! buffer de salida
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
res:scfifo
|
|
generic map (lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 128, lpm_widthu => fd, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
|
|
port map (rdreq => sres_ack, aclr => '0', empty => sres_e, clock => clk, q => sres_q, wrreq => sres_w, data => sres_d(qsc)&sres_d(qx)&sres_d(qy)&sres_d(qz));
|
|
output_buffer:scfifo
|
output_buffer:scfifo
|
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
|
generic map (almost_empty_value => 2**mb,almost_full_value => (2**fd)-52, lpm_widthu => fd, lpm_numwords => 2**fd, lpm_showahead => "ON", lpm_width => 32, overflow_checking => "ON", underflow_checking => "ON", use_eab => "ON")
|
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
|
port map (empty => soutb_e, aclr => '0', clock => clk, rdreq => soutb_ack, wrreq => soutb_w, q => master_writedata, usedw => soutb_usedw, almost_full => soutb_af, almost_empty => soutb_ae, data => soutb_d);
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
|
--! PROCESO DE CONTROL DE FLUJO ENTRE EL BUFFER DE RESULTADOS Y EL BUFFER DE SALIDA
|
--! ******************************************************************************************************************************************************
|
--! ******************************************************************************************************************************************************
|
|
|
FLOW_CONTROL_OUTPUT_STAGE:
|
FLOW_CONTROL_OUTPUT_STAGE:
|
process (clk,rst,master_readdata, master_readdatavalid,sres_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,sres_q,supload_start)
|
process (clk,rst,master_readdata, master_readdatavalid,sr_e,sreg_block(reg_ctrl)(reg_ctrl_vt downto reg_ctrl_sc),sm,supload_chain,zero,ssync_chain_pending,supload_start)
|
begin
|
begin
|
|
|
|
|
--! Compute initial State.
|
--! Compute initial State.
|
|
|
Line 534... |
Line 558... |
if supload_chain=DMA then
|
if supload_chain=DMA then
|
--! Modo DMA escribir los datos de entrada directamente en el buffer.
|
--! Modo DMA escribir los datos de entrada directamente en el buffer.
|
soutb_w <= master_readdatavalid;
|
soutb_w <= master_readdatavalid;
|
else
|
else
|
--!Modo Arithmetic Pipeline
|
--!Modo Arithmetic Pipeline
|
soutb_w <= not(sres_e);
|
soutb_w <= not(sr_e);
|
end if;
|
end if;
|
|
|
--! Control de lectura de la cola de resultados.
|
--! Control de lectura de la cola de resultados.
|
if sres_e='0' then
|
if sr_e='0' then
|
--!Hay datos en la cola de resultados.
|
--!Hay datos en la cola de resultados.
|
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
|
if (supload_chain=UPVZ and sreg_block(reg_ctrl)(reg_ctrl_sc)='0') or supload_chain=SC then
|
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
|
--!Se transfiere el ultimo componente vectorial y no se estan cargando resultados escalares.
|
sres_ack <= '1';
|
sr_ack <= '1';
|
else
|
else
|
sres_ack <= '0';
|
sr_ack <= '0';
|
end if;
|
end if;
|
else
|
else
|
sres_ack <= '0';
|
sr_ack <= '0';
|
end if;
|
end if;
|
|
|
|
|
--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
|
--! Decodificar que salida de la cola de resultados se conecta a la entrada del otput buffer
|
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
|
--! DMA Path Control: Si se encuentra habilitado el modo dma entonces conectar la entrada del buffer de salida a la interconexión
|
case supload_chain is
|
case supload_chain is
|
when UPVX =>
|
when UPVX =>
|
soutb_d <= sres_q (32*qx+31 downto 32*qx);
|
soutb_d <= svx;
|
when UPVY =>
|
when UPVY =>
|
soutb_d <= sres_q (32*qy+31 downto 32*qy);
|
soutb_d <= svy;
|
when UPVZ =>
|
when UPVZ =>
|
soutb_d <= sres_q (32*qz+31 downto 32*qz);
|
soutb_d <= svz;
|
when SC =>
|
when SC =>
|
soutb_d <= sres_q (32*qsc+31 downto 32*qsc);
|
soutb_d <= ssc;
|
when DMA =>
|
when DMA =>
|
soutb_d <= master_readdata;
|
soutb_d <= master_readdata;
|
end case;
|
end case;
|
|
|
|
|
Line 582... |
Line 606... |
supload_chain <= UPVX;
|
supload_chain <= UPVX;
|
elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
elsif clk'event and clk='1' and sreg_block(reg_ctrl)(reg_ctrl_dma)='0' then
|
--! Modo de operación normal.
|
--! Modo de operación normal.
|
case supload_chain is
|
case supload_chain is
|
when UPVX =>
|
when UPVX =>
|
if sres_e='1' then
|
if sr_e='1' then
|
supload_chain <= supload_start;
|
supload_chain <= supload_start;
|
else
|
else
|
supload_chain <= UPVY;
|
supload_chain <= UPVY;
|
end if;
|
end if;
|
when UPVY =>
|
when UPVY =>
|
Line 699... |
Line 723... |
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! AVALON MEMORY MAPPED SLAVE BEGINS => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! AVALON MEMORY MAPPED SLAVE BEGINS => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => => =>
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! *************************************************************************************************************************************************************************************************************************************************************
|
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
--! Master Slave Process: Proceso para la escritura y lectura de registros desde el NIOS II.
|
low_register_bank:
|
low_register_bank:
|
process (clk,rst,sreg_block)
|
process (clk,rst,sreg_block,soutb_w,supload_chain)
|
begin
|
begin
|
if rst=rstMasterValue then
|
if rst=rstMasterValue then
|
for i in reg_scratch00 downto reg_vz loop
|
for i in reg_scratch00 downto reg_vz loop
|
sreg_block(i) <= (others => '0');
|
sreg_block(i) <= (others => '0');
|
end loop;
|
end loop;
|
Line 718... |
Line 742... |
|
|
sslave_address <= slave_address;
|
sslave_address <= slave_address;
|
sslave_write <= slave_write;
|
sslave_write <= slave_write;
|
sslave_read <= slave_read;
|
sslave_read <= slave_read;
|
sslave_writedata <= slave_writedata;
|
sslave_writedata <= slave_writedata;
|
for i in reg_scratch00 downto reg_vz loop
|
|
|
if soutb_w='1' and supload_chain=DMA then
|
|
sreg_block(reg_vx) <= sdx;
|
|
else
|
|
sreg_block(reg_vx) <= sdx;
|
|
|
|
end if;
|
|
if soutb_w='1' and supload_chain=DMA then
|
|
sreg_block(reg_vy) <= sdy;
|
|
else
|
|
sreg_block(reg_vy) <= sdy;
|
|
|
|
end if;
|
|
if soutb_w='1' and supload_chain=DMA then
|
|
sreg_block(reg_scratch00) <= sdz;
|
|
sreg_block(reg_vz) <= sdz;
|
|
else
|
|
sreg_block(reg_scratch00) <= sdz;
|
|
sreg_block(reg_vz) <= sdz;
|
|
end if;
|
|
if soutb_w='1' and supload_chain=DMA then
|
|
sreg_block(reg_scalar) <= sdsc;
|
|
else
|
|
sreg_block(reg_scalar) <= sdsc;
|
|
end if;
|
|
|
|
for i in reg_scratch00-5 downto reg_vz loop
|
if sslave_address=i then
|
if sslave_address=i then
|
if sslave_write='1' then
|
if sslave_write='1' then
|
sreg_block(i) <= sslave_writedata;
|
sreg_block(i) <= sslave_writedata;
|
end if;
|
end if;
|
end if;
|
end if;
|