| Line 198... |
Line 198... |
signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sburstcount_sink : std_logic_vector(mb downto 0);
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signal sflood_condition : std_logic;
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signal sflood_condition : std_logic;
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sflood_burstcount : std_logic_vector(mb downto 0);
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signal sp0,sp1,sp2 : std_logic_vector(31 downto 0);
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signal sp0,sp1,sp2,sp3,sp4,sp5,sp6,sp7,sp8: std_logic_vector(31 downto 0);
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--! Arithmetic Pipeline and Data Path Control
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--! Arithmetic Pipeline and Data Path Control
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component ap_n_dpc
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component ap_n_dpc
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port (
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port (
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p0,p1,p2 : out std_logic_vector(31 downto 0);
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p0,p1,p2,p3,p4,p5,p6,p7,p8 : out std_logic_vector(31 downto 0);
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clk : in std_logic;
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clk : in std_logic;
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rst : in std_logic;
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rst : in std_logic;
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ax : in std_logic_vector(31 downto 0);
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ax : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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ay : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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az : in std_logic_vector(31 downto 0);
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| Line 243... |
Line 243... |
arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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arithmetic_pipeline_and_datapath_controller : ap_n_dpc
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port map (
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port map (
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p0 => sp0,
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p0 => sp0,
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p1 => sp1,
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p1 => sp1,
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p2 => sp2,
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p2 => sp2,
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p3 => sp3,
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p4 => sp4,
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p5 => sp5,
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p6 => sp6,
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p7 => sp7,
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p8 => sp8,
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clk => clk,
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clk => clk,
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rst => rst,
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rst => rst,
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ax => sreg_block(reg_ax),
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ax => sreg_block(reg_ax),
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ay => sreg_block(reg_ay),
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ay => sreg_block(reg_ay),
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az => sreg_block(reg_az),
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az => sreg_block(reg_az),
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| Line 731... |
Line 738... |
sslave_address <= slave_address;
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sslave_address <= slave_address;
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sslave_write <= slave_write;
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sslave_write <= slave_write;
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sslave_read <= slave_read;
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sslave_read <= slave_read;
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sslave_writedata <= slave_writedata;
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sslave_writedata <= slave_writedata;
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sreg_block(reg_vz) <= sp0;
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sreg_block(reg_vy) <= sp1;
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sreg_block(reg_vx) <= sp2;
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for i in reg_scalar downto reg_scalar loop
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for i in reg_scalar downto reg_scalar loop
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if sslave_address=i then
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if sslave_address=i then
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if sslave_write='1' then
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if sslave_write='1' then
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sreg_block(i) <= sslave_writedata;
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sreg_block(i) <= sslave_writedata;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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for i in 15 downto 0 loop
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for i in 15 downto 0 loop
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if sslave_address=i then
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if sslave_address=i then
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if sslave_read='1' then
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if sslave_read='1' then
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if (i<10 and i>3) or i=0 then
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slave_readdata <= sreg_block(i);
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slave_readdata <= sreg_block(i);
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elsif i=1 then
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slave_readdata <= sp0;
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elsif i=2 then
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slave_readdata <= sp1;
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elsif i=3 then
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slave_readdata <= sp2;
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elsif i=10 then
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slave_readdata <= sp3;
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elsif i=11 then
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slave_readdata <= sp4;
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elsif i=12 then
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slave_readdata <= sp5;
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elsif i=13 then
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slave_readdata <= sp6;
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elsif i=14 then
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slave_readdata <= sp7;
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elsif i=15 then
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slave_readdata <= sp8;
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end if;
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end if;
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end if;
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end if;
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end if;
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end loop;
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end loop;
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end if;
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end if;
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end process;
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end process;
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