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URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [branches/] [fp_sgdma/] [raytrac_hw.tcl] - Diff between revs 196 and 218

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Rev 196 Rev 218
Line 1... Line 1... 
# TCL File Generated by Component Editor 11.0
 
# TCL File Generated by Component Editor 11.0
 
# Tue Jun 05 21:33:32 COT 2012
 
# Sun Aug 12 16:47:44 COT 2012
 
# DO NOT MODIFY
 
# DO NOT MODIFY
 
 
 
 
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | 
# | 
# | RayTrAC "RayTrAC" v1.0
 
# | raytrac "raytrac" v1.0
 
# | null 2012.06.05.21:33:32
 
# | null 2012.08.12.16:47:44
 
# | 
# | 
# | 
# | 
# | //IMACJULIAN/imac/Code/Indigo/fp/fp/raytrac.vhd
 
# | J:/code/RtEngineHw/SlaveInterfaceDrive/raytrac/raytrac.vhd
 
# | 
# | 
# |    ./arithpack.vhd syn, sim
 
# |    ./raytrac.vhd syn
 
# |    ./raytrac.vhd syn, sim
 
 
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | request TCL package from ACDS 11.0
 
# | request TCL package from ACDS 11.0
Line 22... Line 21... 
package require -exact sopc 11.0
 
package require -exact sopc 11.0
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | module RayTrAC
 
# | module raytrac
 
# | 
# | 
set_module_property NAME RayTrAC
 
set_module_property NAME raytrac
 
set_module_property VERSION 1.0
 
set_module_property VERSION 1.0
 
set_module_property INTERNAL false
 
set_module_property INTERNAL false
 
set_module_property OPAQUE_ADDRESS_MAP true
 
set_module_property OPAQUE_ADDRESS_MAP true
 
set_module_property GROUP "Arithmetic RayTrac Components"
 
set_module_property DISPLAY_NAME raytrac
 
set_module_property DISPLAY_NAME RayTrAC
 
 
 
set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd
 
set_module_property TOP_LEVEL_HDL_FILE raytrac.vhd
 
set_module_property TOP_LEVEL_HDL_MODULE raytrac
 
set_module_property TOP_LEVEL_HDL_MODULE raytrac
 
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
 
set_module_property EDITABLE true
 
set_module_property EDITABLE true
 
set_module_property ANALYZE_HDL TRUE
 
set_module_property ANALYZE_HDL TRUE
Line 43... Line 41... 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | files
 
# | files
 
# | 
# | 
add_file arithpack.vhd {SYNTHESIS SIMULATION}
 
add_file raytrac.vhd SYNTHESIS
 
add_file raytrac.vhd {SYNTHESIS SIMULATION}
 
 
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | parameters
 
# | parameters
 
# | 
# | 
 
 
add_parameter wd INTEGER 32
 
 
 
set_parameter_property wd DEFAULT_VALUE 32
 
 
 
set_parameter_property wd DISPLAY_NAME wd
 
 
 
set_parameter_property wd TYPE INTEGER
 
 
 
set_parameter_property wd UNITS None
 
 
 
set_parameter_property wd ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property wd AFFECTS_GENERATION false
 
 
 
set_parameter_property wd HDL_PARAMETER true
 
 
 
add_parameter sl INTEGER 5
 
 
 
set_parameter_property sl DEFAULT_VALUE 5
 
 
 
set_parameter_property sl DISPLAY_NAME sl
 
 
 
set_parameter_property sl TYPE INTEGER
 
 
 
set_parameter_property sl UNITS None
 
 
 
set_parameter_property sl ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property sl AFFECTS_GENERATION false
 
 
 
set_parameter_property sl HDL_PARAMETER true
 
 
 
add_parameter ln INTEGER 12
 
 
 
set_parameter_property ln DEFAULT_VALUE 12
 
 
 
set_parameter_property ln DISPLAY_NAME ln
 
 
 
set_parameter_property ln TYPE INTEGER
 
 
 
set_parameter_property ln UNITS None
 
 
 
set_parameter_property ln ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property ln AFFECTS_GENERATION false
 
 
 
set_parameter_property ln HDL_PARAMETER true
 
 
 
add_parameter fd INTEGER 8
 
 
 
set_parameter_property fd DEFAULT_VALUE 8
 
 
 
set_parameter_property fd DISPLAY_NAME fd
 
 
 
set_parameter_property fd TYPE INTEGER
 
 
 
set_parameter_property fd UNITS None
 
 
 
set_parameter_property fd ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property fd AFFECTS_GENERATION false
 
 
 
set_parameter_property fd HDL_PARAMETER true
 
 
 
add_parameter mb INTEGER 3
 
 
 
set_parameter_property mb DEFAULT_VALUE 3
 
 
 
set_parameter_property mb DISPLAY_NAME mb
 
 
 
set_parameter_property mb TYPE INTEGER
 
 
 
set_parameter_property mb UNITS None
 
 
 
set_parameter_property mb ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property mb AFFECTS_GENERATION false
 
 
 
set_parameter_property mb HDL_PARAMETER true
 
 
 
add_parameter nr INTEGER 3
 
 
 
set_parameter_property nr DEFAULT_VALUE 3
 
 
 
set_parameter_property nr DISPLAY_NAME nr
 
 
 
set_parameter_property nr TYPE INTEGER
 
 
 
set_parameter_property nr UNITS None
 
 
 
set_parameter_property nr ALLOWED_RANGES -2147483648:2147483647
 
 
 
set_parameter_property nr AFFECTS_GENERATION false
 
 
 
set_parameter_property nr HDL_PARAMETER true
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | display items
 
# | display items
 
# | 
# | 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | connection point clock
 
# | connection point rtClock
 
# | 
# | 
add_interface clock clock end
 
add_interface rtClock clock end
 
set_interface_property clock clockRate 0
 
set_interface_property rtClock clockRate 0
 
 
 
 
 
set_interface_property clock ENABLED true
 
set_interface_property rtClock ENABLED true
 
 
 
 
 
add_interface_port clock clk clk Input 1
 
add_interface_port rtClock clk clk Input 1
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | connection point avalon_slave_0
 
# | connection point rtSlave
 
# | 
# | 
add_interface avalon_slave_0 avalon end
 
add_interface rtSlave avalon end
 
set_interface_property avalon_slave_0 addressAlignment DYNAMIC
 
set_interface_property rtSlave addressAlignment DYNAMIC
 
set_interface_property avalon_slave_0 addressUnits WORDS
 
set_interface_property rtSlave addressUnits WORDS
 
set_interface_property avalon_slave_0 associatedClock clock
 
set_interface_property rtSlave associatedClock rtClock
 
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false
 
set_interface_property rtSlave associatedReset rtReset
 
set_interface_property avalon_slave_0 explicitAddressSpan 0
 
set_interface_property rtSlave burstOnBurstBoundariesOnly false
 
set_interface_property avalon_slave_0 holdTime 0
 
set_interface_property rtSlave explicitAddressSpan 0
 
set_interface_property avalon_slave_0 isMemoryDevice false
 
set_interface_property rtSlave holdTime 0
 
set_interface_property avalon_slave_0 isNonVolatileStorage false
 
set_interface_property rtSlave isMemoryDevice false
 
set_interface_property avalon_slave_0 linewrapBursts false
 
set_interface_property rtSlave isNonVolatileStorage false
 
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0
 
set_interface_property rtSlave linewrapBursts false
 
set_interface_property avalon_slave_0 printableDevice false
 
set_interface_property rtSlave maximumPendingReadTransactions 0
 
set_interface_property avalon_slave_0 readLatency 0
 
set_interface_property rtSlave printableDevice false
 
set_interface_property avalon_slave_0 readWaitTime 1
 
set_interface_property rtSlave readLatency 2
 
set_interface_property avalon_slave_0 setupTime 0
 
set_interface_property rtSlave readWaitStates 0
 
set_interface_property avalon_slave_0 timingUnits Cycles
 
set_interface_property rtSlave readWaitTime 0
 
set_interface_property avalon_slave_0 writeWaitTime 0
 
set_interface_property rtSlave setupTime 0
 
 
 
set_interface_property rtSlave timingUnits Cycles
 
 
 
set_interface_property rtSlave writeWaitTime 0
 
 
 
 
 
set_interface_property avalon_slave_0 ENABLED true
 
set_interface_property rtSlave ENABLED true
 
 
 
 
 
add_interface_port avalon_slave_0 wr write Input 1
 
add_interface_port rtSlave slave_address address Input 4
 
add_interface_port avalon_slave_0 add address Input 13
 
add_interface_port rtSlave slave_read read Input 1
 
add_interface_port avalon_slave_0 d writedata Input 32
 
add_interface_port rtSlave slave_write write Input 1
 
add_interface_port avalon_slave_0 q readdata Output 32
 
add_interface_port rtSlave slave_readdata readdata Output 32
 
add_interface_port avalon_slave_0 rd read Input 1
 
add_interface_port rtSlave slave_writedata writedata Input 32
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | connection point reset_sink
 
# | connection point rtReset
 
# | 
# | 
add_interface reset_sink reset end
 
add_interface rtReset reset end
 
set_interface_property reset_sink associatedClock clock
 
set_interface_property rtReset associatedClock rtClock
 
set_interface_property reset_sink synchronousEdges DEASSERT
 
set_interface_property rtReset synchronousEdges BOTH
 
 
 
 
 
set_interface_property reset_sink ENABLED true
 
set_interface_property rtReset ENABLED true
 
 
 
 
 
add_interface_port reset_sink rst reset_n Input 1
 
add_interface_port rtReset rst reset_n Input 1
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
# +-----------------------------------
 
# +-----------------------------------
 
# | connection point interrupt_sender_1
 
# | connection point rtMaster
 
# | 
# | 
add_interface interrupt_sender_1 interrupt end
 
add_interface rtMaster avalon start
 
set_interface_property interrupt_sender_1 associatedAddressablePoint avalon_slave_0
 
set_interface_property rtMaster addressUnits SYMBOLS
 
set_interface_property interrupt_sender_1 associatedClock clock
 
set_interface_property rtMaster associatedClock rtClock
 
 
 
set_interface_property rtMaster associatedReset rtReset
 
 
 
set_interface_property rtMaster burstOnBurstBoundariesOnly false
 
 
 
set_interface_property rtMaster doStreamReads false
 
 
 
set_interface_property rtMaster doStreamWrites false
 
 
 
set_interface_property rtMaster linewrapBursts false
 
 
 
set_interface_property rtMaster readLatency 0
 
 
 
 
 
set_interface_property interrupt_sender_1 ENABLED true
 
set_interface_property rtMaster ENABLED true
 
 
 
 
 
add_interface_port interrupt_sender_1 irq irq Output 1
 
add_interface_port rtMaster master_burstcount burstcount Output 5
 
 
 
add_interface_port rtMaster master_waitrequest waitrequest Input 1
 
 
 
add_interface_port rtMaster master_read read Output 1
 
 
 
add_interface_port rtMaster master_readdata readdata Input 32
 
 
 
add_interface_port rtMaster master_readdatavalid readdatavalid Input 1
 
 
 
add_interface_port rtMaster master_write write Output 1
 
 
 
add_interface_port rtMaster master_writedata writedata Output 32
 
 
 
add_interface_port rtMaster master_address address Output 32
 
 
 
# | 
 
 
# +-----------------------------------
 
 
 
 
 
 
 
# +-----------------------------------
 
 
 
# | connection point interrupt_sender
 
 
 
# | 
 
 
add_interface interrupt_sender interrupt end
 
 
 
set_interface_property interrupt_sender associatedAddressablePoint rtSlave
 
 
 
set_interface_property interrupt_sender associatedClock rtClock
 
 
 
set_interface_property interrupt_sender associatedReset rtReset
 
 
 
 
 
 
 
set_interface_property interrupt_sender ENABLED true
 
 
 
 
 
 
 
add_interface_port interrupt_sender irq irq Output 1
 
# | 
# | 
# +-----------------------------------
 
# +-----------------------------------
 
 
 
 
 
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