OpenCores
URL https://opencores.org/ocsvn/raytrac/raytrac/trunk

Subversion Repositories raytrac

[/] [raytrac/] [trunk/] [sqrtdiv/] [shifter2xstage.vhd] - Diff between revs 60 and 67

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 60 Rev 67
Line 35... Line 35...
        );
        );
        port (
        port (
                data    : in std_logic_vector (width-1 downto 0);
                data    : in std_logic_vector (width-1 downto 0);
                exp             : out std_logic_vector (2*integer(ceil(log(real(width),2.0)))-1 downto 0);
                exp             : out std_logic_vector (2*integer(ceil(log(real(width),2.0)))-1 downto 0);
                add             : out std_logic_vector (2*address_width-1 downto 0);
                add             : out std_logic_vector (2*address_width-1 downto 0);
                zero    : out std_logic_vector (1 downto 0)
                zero    : out std_logic
        );
        );
end shifter2xstage;
end shifter2xstage;
 
 
architecture shifter2xstage_arch of shifter2xstage is
architecture shifter2xstage_arch of shifter2xstage is
 
 
        signal exp0     : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
        signal exp0     : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
        signal exp1     : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
        signal exp1     : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
        signal add0     : std_logic_vector (address_width-1 downto 0);
        signal add0     : std_logic_vector (address_width-1 downto 0);
        signal add1     : std_logic_vector (address_width-1 downto 0);
        signal add1     : std_logic_vector (address_width-1 downto 0);
 
        signal szero: std_logic_vector (1 downto 0);
 
 
begin
begin
 
        zero <= szero(1) and szero(0);
        evenS:shifter
        evenS:shifter
        generic map (address_width,width,"YES")
        generic map (address_width,width,"YES")
        port map (data,exp0,add0,zero(0));
        port map (data,exp0,add0,szero(0));
        oddS:shifter
        oddS:shifter
        generic map (address_width,width,"NO")
        generic map (address_width,width,"NO")
        port map (data,exp1,add1,zero(1));
        port map (data,exp1,add1,szero(1));
        exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
        exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
        exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
        exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
        add(address_width-1 downto 0)<=add0;
        add(address_width-1 downto 0)<=add0;
        add(2*address_width-1 downto address_width)<=add1;
        add(2*address_width-1 downto address_width)<=add1;
end shifter2xstage_arch;
end shifter2xstage_arch;

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.