Line 35... |
Line 35... |
);
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);
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port (
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port (
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data : in std_logic_vector (width-1 downto 0);
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data : in std_logic_vector (width-1 downto 0);
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exp : out std_logic_vector (2*integer(ceil(log(real(width),2.0)))-1 downto 0);
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exp : out std_logic_vector (2*integer(ceil(log(real(width),2.0)))-1 downto 0);
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add : out std_logic_vector (2*address_width-1 downto 0);
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add : out std_logic_vector (2*address_width-1 downto 0);
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zero : out std_logic_vector (1 downto 0)
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zero : out std_logic
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);
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);
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end shifter2xstage;
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end shifter2xstage;
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architecture shifter2xstage_arch of shifter2xstage is
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architecture shifter2xstage_arch of shifter2xstage is
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signal exp0 : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
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signal exp0 : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
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signal exp1 : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
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signal exp1 : std_logic_vector (integer(ceil(log(real(width),2.0)))-1 downto 0);
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signal add0 : std_logic_vector (address_width-1 downto 0);
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signal add0 : std_logic_vector (address_width-1 downto 0);
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signal add1 : std_logic_vector (address_width-1 downto 0);
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signal add1 : std_logic_vector (address_width-1 downto 0);
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signal szero: std_logic_vector (1 downto 0);
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begin
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begin
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zero <= szero(1) and szero(0);
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evenS:shifter
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evenS:shifter
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generic map (address_width,width,"YES")
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generic map (address_width,width,"YES")
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port map (data,exp0,add0,zero(0));
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port map (data,exp0,add0,szero(0));
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oddS:shifter
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oddS:shifter
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generic map (address_width,width,"NO")
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generic map (address_width,width,"NO")
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port map (data,exp1,add1,zero(1));
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port map (data,exp1,add1,szero(1));
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exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
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exp(integer(ceil(log(real(width),2.0)))-1 downto 0)<=exp0;
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exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
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exp(2*integer(ceil(log(real(width),2.0)))-1 downto integer(ceil(log(real(width),2.0))))<=exp1;
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add(address_width-1 downto 0)<=add0;
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add(address_width-1 downto 0)<=add0;
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add(2*address_width-1 downto address_width)<=add1;
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add(2*address_width-1 downto address_width)<=add1;
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end shifter2xstage_arch;
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end shifter2xstage_arch;
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