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//// ////
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//// Author: Eyal Hochberg ////
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//// eyal@provartec.com ////
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//// ////
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//// Downloaded from: http://www.opencores.org ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2010 Provartec LTD ////
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//// www.provartec.com ////
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//// info@provartec.com ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation.////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more////
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//// details. http://www.gnu.org/licenses/lgpl.html ////
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//// ////
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//////////////////////////////////////////////////////////////////##>
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INCLUDE def_axi2apb_static.txt
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INCLUDE def_axi2apb_static.txt
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SWAP #FFD #1 ## flip-flop delay
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SWAP #FFD #1 ## flip-flop delay
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SWAP PREFIX soc ## prefix for all modules and file names
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SWAP PREFIX soc ## prefix for all modules and file names
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SWAP SLAVE_NUM 8 ## number of APB slaves
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SWAP SLAVE_NUM 8 ## number of APB slaves
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SWAP CMD_DEPTH 2 ## number of AXI command FIFO
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SWAP CMD_DEPTH 2 ## number of AXI command FIFO
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SWAP ADDR_BITS 24 ## AXI and APB address bits
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SWAP ADDR_BITS 24 ## AXI and APB address bits
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SWAP ID_BITS 4 ## AXI ID bits
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SWAP ID_BITS 4 ## AXI ID bits
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SWAP DEC_BITS 8 ## Address MSBits for slave decoding
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SWAP DEC_BITS 8 ## Address MSBits for slave decoding
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SWAP DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
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SWAP DEC_ADDR0 DEC_BITS'h00 ## Slave 0 address deciding
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SWAP DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
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SWAP DEC_ADDR1 DEC_BITS'h01 ## Slave 1 address deciding
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SWAP DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
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SWAP DEC_ADDR2 DEC_BITS'h02 ## Slave 2 address deciding
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SWAP DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
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SWAP DEC_ADDR3 DEC_BITS'h03 ## Slave 3 address deciding
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SWAP DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
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SWAP DEC_ADDR4 DEC_BITS'h10 ## Slave 4 address deciding
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SWAP DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
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SWAP DEC_ADDR5 DEC_BITS'h11 ## Slave 5 address deciding
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SWAP DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
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SWAP DEC_ADDR6 DEC_BITS'h12 ## Slave 6 address deciding
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SWAP DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
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SWAP DEC_ADDR7 DEC_BITS'h13 ## Slave 7 address deciding
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