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Line 38... |
constant UART_START : std_logic := '0';
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constant UART_START : std_logic := '0';
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constant PARITY_EN : std_logic := '1';
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constant PARITY_EN : std_logic := '1';
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constant RST_LVL : std_logic := '1';
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constant RST_LVL : std_logic := '1';
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-- Types
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-- Types
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type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap
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type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap signals
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-- Signals
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-- RX Signals
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signal rx_fsm : state; -- Control of reception
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signal rx_fsm : state; -- Control of reception
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signal tx_fsm : state; -- Control of transmission
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signal rx_clk_en : std_logic; -- Received clock enable
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signal clock_en : std_logic; -- Internal clock enable
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signal rx_rcv_init : std_logic; -- Start of reception
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signal rx_par_bit : std_logic; -- Calculated Parity bit
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-- RX Data Temp
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signal rx_data_tmp : std_logic_vector(7 downto 0); -- Serial to parallel converter
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signal rx_par_bit : std_logic;
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signal rx_data_cnt : std_logic_vector(2 downto 0); -- Count received bits
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signal rx_data_tmp : std_logic_vector(7 downto 0);
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signal rx_data_cnt : std_logic_vector(2 downto 0);
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-- TX Data Temp
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-- TX Signals
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signal tx_par_bit : std_logic;
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signal tx_fsm : state; -- Control of transmission
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signal tx_data_tmp : std_logic_vector(7 downto 0);
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signal tx_clk_en : std_logic; -- Transmited clock enable
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signal tx_data_cnt : std_logic_vector(2 downto 0);
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signal tx_par_bit : std_logic; -- Calculated Parity bit
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signal tx_data_tmp : std_logic_vector(7 downto 0); -- Parallel to serial converter
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signal tx_data_cnt : std_logic_vector(2 downto 0); -- Count transmited bits
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begin
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begin
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clock_manager:process(clk)
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tx_clk_gen:process(clk)
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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-- Normal Operation
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-- Normal Operation
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if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
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if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 then
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clock_en <= '1';
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tx_clk_en <= '1';
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counter := 0;
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counter := 0;
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else
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else
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clock_en <= '0';
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tx_clk_en <= '0';
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counter := counter + 1;
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counter := counter + 1;
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end if;
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end if;
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-- Reset condition
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-- Reset condition
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if rst = RST_LVL then
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if rst = RST_LVL then
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tx_clk_en := '0';
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counter := 0;
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counter := 0;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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tx_proc:process(clk)
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tx_proc:process(clk)
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variable data_cnt : std_logic_vector(2 downto 0);
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variable data_cnt : std_logic_vector(2 downto 0);
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if clock_en = '1' then
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if tx_clk_en = '1' then
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-- Default values
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-- Default values
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tx_end <= '0';
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tx_end <= '0';
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tx <= UART_IDLE;
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tx <= UART_IDLE;
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-- FSM description
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-- FSM description
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case tx_fsm is
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case tx_fsm is
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| Line 138... |
Line 139... |
end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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rx_start_detect:process(clk)
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variable deb_buf : std_logic_vector(3 downto 0);
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variable deb_val : std_logic;
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variable deb_old : std_logic;
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begin
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if clk'event and clk = '1' then
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-- Store previous debounce value
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deb_old := deb_val;
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-- Debounce logic
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if deb_buf = "0000" then
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deb_val := '0';
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elsif deb_buf = "1111" then
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deb_val := '1';
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end if;
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-- Data storage to debounce
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deb_buf := deb_buf(2 downto 0) & rx;
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-- Check RX idle state
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if rx_fsm = idle then
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-- Falling edge detection
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if deb_old = '1' and deb_val = '0' then
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rx_rcv_init <= '1';
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end if;
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-- Default assignments
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else
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rx_rcv_init <= '0';
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end if;
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-- Reset condition
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if rst = RST_LVL then
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deb_old := '0';
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deb_val := '0';
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deb_buf <= (others=>'0');
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rx_rcv_init <= '0';
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end if;
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end if;
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end if;
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rx_clk_gen:process(clk)
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variable counter : integer range 0 to conv_integer((CLK_FREQ*1_000_000)/SER_FREQ-1);
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begin
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if clk'event and clk = '1' then
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-- Normal Operation
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if counter = (CLK_FREQ*1_000_000)/SER_FREQ-1 and rx_rcv_init = '1' then
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rx_clk_en <= '1';
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counter := 0;
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else
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rx_clk_en <= '0';
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counter := counter + 1;
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end if;
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-- Reset condition
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if rst = RST_LVL then
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rx_clk_en <= '0';
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counter := 0;
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end if;
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end if;
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end process;
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rx_proc:process(clk)
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rx_proc:process(clk)
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begin
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begin
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if clk'event and clk = '1' then
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if clk'event and clk = '1' then
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if clock_en = '1' then
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if rx_clk_en = '1' then
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-- Default values
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-- Default values
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rx_ready <= '0';
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rx_ready <= '0';
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-- FSM description
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-- FSM description
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case rx_fsm is
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case rx_fsm is
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-- Wait to transfer data
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-- Wait to transfer data
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when idle =>
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when idle =>
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if rx = UART_START then
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if rx_rcv_init = '1' then
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rx_fsm <= data;
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rx_fsm <= data;
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end if;
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end if;
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rx_par_bit <= '0';
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rx_par_bit <= '0';
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rx_data_cnt <= (others=>'0');
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rx_data_cnt <= (others=>'0');
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-- Data receive
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-- Data receive
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