URL
https://opencores.org/ocsvn/soc_maker/soc_maker/trunk
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Rev 10 |
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SOCM_CORE
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SOCM_CORE
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name: adv_debug_sys
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name: Advanced Debug System
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description: Advanced Debug System
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description: Advanced Debug System
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version: ads_3
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id: adv_debug_sys,ads_3
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license: LGPL
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license: LGPL
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licensefile:
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licensefile:
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author:
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author:
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authormail:
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authormail:
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vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
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vccmd: svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/tags/ADS_RELEASE_3_0_0/Hardware/adv_dbg_if/rtl rtl
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:jtag: SOCM_IFC
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:jtag: SOCM_IFC
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name: jtag_tap
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name: jtag_tap
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dir: 1
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dir: 1
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version: "1"
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id: jtag_tap,1
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ports:
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ports:
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:tck_i: SOCM_PORT
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:tck_i: SOCM_PORT
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len: 1
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len: 1
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defn: tck
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defn: tck
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:tdi_i: SOCM_PORT
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:tdi_i: SOCM_PORT
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:wb_ifc: SOCM_IFC
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:wb_ifc: SOCM_IFC
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name: wishbone_ma
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name: wishbone_ma
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dir: 1
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dir: 1
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version: "b3"
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id: wishbone_ma,b3
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ports:
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ports:
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:wb_clk_i: SOCM_PORT
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:wb_clk_i: SOCM_PORT
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len: 1
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len: 1
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defn: clk
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defn: clk
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:wb_rst_i: SOCM_PORT
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:wb_rst_i: SOCM_PORT
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len: 2
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len: 2
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:cpu0_dbg_clk: SOCM_IFC
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:cpu0_dbg_clk: SOCM_IFC
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name: clk
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name: clk
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dir: 1
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dir: 1
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version: "1"
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id: clk,1
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ports:
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ports:
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:cpu0_clk_i: SOCM_PORT
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:cpu0_clk_i: SOCM_PORT
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len: 1
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len: 1
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defn: clk
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defn: clk
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:cpu0_dbg_rst: SOCM_IFC
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:cpu0_dbg_rst: SOCM_IFC
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name: rst
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name: rst
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dir: 0
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dir: 0
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version: "1"
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id: rst,1
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ports:
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ports:
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:cpu0_rst_o: SOCM_PORT
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:cpu0_rst_o: SOCM_PORT
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len: 1
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len: 1
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defn: rst
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defn: rst
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:cpu0_dbg: SOCM_IFC
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:cpu0_dbg: SOCM_IFC
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name: debug
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name: debug
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dir: 0
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dir: 0
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version: "1"
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id: debug,1
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ports:
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ports:
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:cpu0_addr_o: SOCM_PORT
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:cpu0_addr_o: SOCM_PORT
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len: 32
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len: 32
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defn: dbg_adr
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defn: dbg_adr
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:cpu0_data_o: SOCM_PORT
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:cpu0_data_o: SOCM_PORT
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