Subversion Repositories soc_maker

SOCM_CORE

SOCM_CORE

description: OpenRISC CPU

description: OpenRISC CPU

license: LGPL

license: LGPL

licensefile:

licensefile:

author:

author:

authormail:

authormail:

vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl

vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/tags/or1200/rel2/rtl rtl

toplevel: or1200_top

toplevel: or1200_top

interfaces:

interfaces:

  :clmode: SOCM_IFC

  :clmode: SOCM_IFC

    name: single

    name: single

    dir: 1

    dir: 1

    ports:

    ports:

      :clmode_i: SOCM_PORT

      :clmode_i: SOCM_PORT

        len: 2

        len: 2

        defn: single

        defn: single

  :pic_ints: SOCM_IFC

  :pic_ints: SOCM_IFC

    name: single

    name: single

    dir: 1

    dir: 1

    ports:

    ports:

      :pic_ints_i: SOCM_PORT

      :pic_ints_i: SOCM_PORT

        len: 20

        len: 20

        defn: single

        defn: single

  :clk: SOCM_IFC

  :clk: SOCM_IFC

    name: clk

    name: clk

    dir: 1

    dir: 1

    ports:

    ports:

      :clk_i: SOCM_PORT

      :clk_i: SOCM_PORT

        len: 1

        len: 1

        defn: clk

        defn: clk

  :rst: SOCM_IFC

  :rst: SOCM_IFC

    name: rst

    name: rst

    dir: 1

    dir: 1

    ports:

    ports:

      :rst_i: SOCM_PORT

      :rst_i: SOCM_PORT

        len: 1

        len: 1

        defn: rst

        defn: rst

  :wb_instruction: SOCM_IFC

  :wb_instruction: SOCM_IFC

    name: wishbone_ma

    name: wishbone_ma

    dir: 1

    dir: 1

    ports:

    ports:

      :iwb_clk_i: SOCM_PORT

      :iwb_clk_i: SOCM_PORT

        defn: clk

        defn: clk

        len:  1

        len:  1

      :iwb_rst_i: SOCM_PORT

      :iwb_rst_i: SOCM_PORT

        len:  1

        len:  1

  :wb_data: SOCM_IFC

  :wb_data: SOCM_IFC

    name: wishbone_ma

    name: wishbone_ma

    dir: 1

    dir: 1

    ports:

    ports:

      :dwb_clk_i: SOCM_PORT

      :dwb_clk_i: SOCM_PORT

        defn: clk

        defn: clk

        len:  1

        len:  1

      :dwb_rst_i: SOCM_PORT

      :dwb_rst_i: SOCM_PORT

        len:  1

        len:  1

  :ext_debug: SOCM_IFC

  :ext_debug: SOCM_IFC

    name: debug

    name: debug

    dir: 1

    dir: 1

    ports:

    ports:

      :dbg_stall_i: SOCM_PORT

      :dbg_stall_i: SOCM_PORT

        defn: dbg_stall

        defn: dbg_stall

        len: 1

        len: 1

      :dbg_ewt_i: SOCM_PORT

      :dbg_ewt_i: SOCM_PORT

        defn: dbg_ack

        defn: dbg_ack

  :pow_man: SOCM_IFC

  :pow_man: SOCM_IFC

    name: or_power_management

    name: or_power_management

    dir: 1

    dir: 1

    ports:

    ports:

      :pm_cpustall_i: SOCM_PORT

      :pm_cpustall_i: SOCM_PORT

         len: 1

         len: 1

         defn: pm_cpustall

         defn: pm_cpustall

      :pm_clksd_o: SOCM_PORT

      :pm_clksd_o: SOCM_PORT