OpenCores

URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [ram_wb/] [ram_wb.yaml] - Diff between revs 8 and 10

Show entire file | Details | Blame | View Log

Rev 8	Rev 10
Line 1...	Line 1...
`SOCM_CORE`	`SOCM_CORE`
`name: ram_wb`	`name: Wishbone RAM`
`description: Onchip-RAM`	`description: Onchip-RAM`
`version: b3`	`id: ram_wb,b3`
`license: LGPL`	`license: LGPL`
`licensefile:`	`licensefile:`
`author:`	`author:`
`authormail:`	`authormail:`
`vccmd:`	`vccmd:`
`toplevel: ram_wb_b3`	`toplevel: ram_wb_b3`

`interfaces:`	`interfaces:`
`:wb_ifc: SOCM_IFC`	`:wb_ifc: SOCM_IFC`
`name: wishbone_sl`	`name: Wishbone IFC`
`dir: 1`	`dir: 1`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:wb_adr_i: SOCM_PORT`	`:wb_adr_i: SOCM_PORT`
`len: 32`	`len: 32`
`defn: adr`	`defn: adr`
`:wb_bte_i: SOCM_PORT`	`:wb_bte_i: SOCM_PORT`

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.