OpenCores
URL https://opencores.org/ocsvn/soc_maker/soc_maker/trunk

Subversion Repositories soc_maker

[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [ram_wb/] [ram_wb.yaml] - Diff between revs 7 and 8

Go to most recent revision | Only display areas with differences | Details | Blame | View Log

Rev 7 Rev 8
SOCM_CORE
SOCM_CORE
name: ram_wb
name: ram_wb
description: Onchip-RAM
description: Onchip-RAM
version: b3
version: b3
license: LGPL
license: LGPL
licensefile:
licensefile:
author:
author:
authormail:
authormail:
vccmd: svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2/rtl/verilog/ram_wb@655 rtl
vccmd:
toplevel: ram_wb_b3
toplevel: ram_wb_b3
interfaces:
interfaces:
  :wb_ifc: SOCM_IFC
  :wb_ifc: SOCM_IFC
    name: wishbone_sl
    name: wishbone_sl
    dir: 1
    dir: 1
    version: "b3"
    version: "b3"
    ports:
    ports:
      :wb_adr_i: SOCM_PORT
      :wb_adr_i: SOCM_PORT
        len: 32
        len: 32
        defn: adr
        defn: adr
      :wb_bte_i: SOCM_PORT
      :wb_bte_i: SOCM_PORT
        len: 2
        len: 2
        defn: bte
        defn: bte
      :wb_cti_i: SOCM_PORT
      :wb_cti_i: SOCM_PORT
        len: 3
        len: 3
        defn: cti
        defn: cti
      :wb_cyc_i: SOCM_PORT
      :wb_cyc_i: SOCM_PORT
        len: 1
        len: 1
        defn: cyc
        defn: cyc
      :wb_dat_i: SOCM_PORT
      :wb_dat_i: SOCM_PORT
        len: 32
        len: 32
        defn: dat_o
        defn: dat_o
      :wb_sel_i: SOCM_PORT
      :wb_sel_i: SOCM_PORT
        len: 4
        len: 4
        defn: sel
        defn: sel
      :wb_stb_i: SOCM_PORT
      :wb_stb_i: SOCM_PORT
        len: 1
        len: 1
        defn: stb
        defn: stb
      :wb_we_i: SOCM_PORT
      :wb_we_i: SOCM_PORT
        len: 1
        len: 1
        defn: we
        defn: we
      :wb_ack_o: SOCM_PORT
      :wb_ack_o: SOCM_PORT
        len: 1
        len: 1
        defn: ack
        defn: ack
      :wb_err_o: SOCM_PORT
      :wb_err_o: SOCM_PORT
        len: 1
        len: 1
        defn: err
        defn: err
      :wb_rty_o: SOCM_PORT
      :wb_rty_o: SOCM_PORT
        len: 1
        len: 1
        defn: rty
        defn: rty
      :wb_dat_o: SOCM_PORT
      :wb_dat_o: SOCM_PORT
        len: 32
        len: 32
        defn: dat_i
        defn: dat_i
      :wb_clk_i: SOCM_PORT
      :wb_clk_i: SOCM_PORT
        len: 1
        len: 1
        defn: clk
        defn: clk
      :wb_rst_i: SOCM_PORT
      :wb_rst_i: SOCM_PORT
        len: 1
        len: 1
        defn: rst
        defn: rst
 
 
hdlfiles:
static_parameters:
  :ram_wb_b3: SOCM_HDL_FILE
  :ram_wb_b3: SOCM_SPARAM
    use_syn: true
    dir: .
    use_sim: true
    path: ./ram_wb_b3.v.in
    type: verilog
    file_dst: ram_wb_b3.v
    path: rtl/ram_wb_b3.v
    parameters:
 
 
 
      :MEM_SIZE: SOCM_SENTRY
 
         token: TOK_MEM_SIZE
 
         type:  integer
 
         visible: true
 
         editable: true
 
         default: 20
 
 
 
      :MEM_ADR_WIDTH: SOCM_SENTRY
 
         token: TOK_MEM_ADR_WIDTH
 
         type:  integer
 
         visible: true
 
         editable: true
 
         default: 15
 
 
 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.