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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [wb_connect/] [minsoc_tc_top.v] - Diff between revs 5 and 7

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Rev 5 Rev 7
Line 96... Line 96... 
//
 
//
 
module minsoc_tc_top (
 
module minsoc_tc_top (
 
        wb_clk_i,
 
        wb_clk_i,
 
        wb_rst_i,
 
        wb_rst_i,
 
 
 
 
 
 
 
   i0_wb_clk_o,
 
 
 
   i0_wb_rst_o,
 
        i0_wb_cyc_i,
 
        i0_wb_cyc_i,
 
        i0_wb_stb_i,
 
        i0_wb_stb_i,
 
        i0_wb_adr_i,
 
        i0_wb_adr_i,
 
        i0_wb_sel_i,
 
        i0_wb_sel_i,
 
        i0_wb_we_i,
 
        i0_wb_we_i,
 
        i0_wb_dat_i,
 
        i0_wb_dat_i,
 
        i0_wb_dat_o,
 
        i0_wb_dat_o,
 
        i0_wb_ack_o,
 
        i0_wb_ack_o,
 
        i0_wb_err_o,
 
        i0_wb_err_o,
 
 
 
 
 
 
 
   i1_wb_clk_o,
 
 
 
   i1_wb_rst_o,
 
        i1_wb_cyc_i,
 
        i1_wb_cyc_i,
 
        i1_wb_stb_i,
 
        i1_wb_stb_i,
 
        i1_wb_adr_i,
 
        i1_wb_adr_i,
 
        i1_wb_sel_i,
 
        i1_wb_sel_i,
 
        i1_wb_we_i,
 
        i1_wb_we_i,
 
        i1_wb_dat_i,
 
        i1_wb_dat_i,
 
        i1_wb_dat_o,
 
        i1_wb_dat_o,
 
        i1_wb_ack_o,
 
        i1_wb_ack_o,
 
        i1_wb_err_o,
 
        i1_wb_err_o,
 
 
 
 
 
 
 
   i2_wb_clk_o,
 
 
 
   i2_wb_rst_o,
 
        i2_wb_cyc_i,
 
        i2_wb_cyc_i,
 
        i2_wb_stb_i,
 
        i2_wb_stb_i,
 
        i2_wb_adr_i,
 
        i2_wb_adr_i,
 
        i2_wb_sel_i,
 
        i2_wb_sel_i,
 
        i2_wb_we_i,
 
        i2_wb_we_i,
 
        i2_wb_dat_i,
 
        i2_wb_dat_i,
 
        i2_wb_dat_o,
 
        i2_wb_dat_o,
 
        i2_wb_ack_o,
 
        i2_wb_ack_o,
 
        i2_wb_err_o,
 
        i2_wb_err_o,
 
 
 
 
 
 
 
   i3_wb_clk_o,
 
 
 
   i3_wb_rst_o,
 
        i3_wb_cyc_i,
 
        i3_wb_cyc_i,
 
        i3_wb_stb_i,
 
        i3_wb_stb_i,
 
        i3_wb_adr_i,
 
        i3_wb_adr_i,
 
        i3_wb_sel_i,
 
        i3_wb_sel_i,
 
        i3_wb_we_i,
 
        i3_wb_we_i,
 
        i3_wb_dat_i,
 
        i3_wb_dat_i,
 
        i3_wb_dat_o,
 
        i3_wb_dat_o,
 
        i3_wb_ack_o,
 
        i3_wb_ack_o,
 
        i3_wb_err_o,
 
        i3_wb_err_o,
 
 
 
 
 
 
 
   i4_wb_clk_o,
 
 
 
   i4_wb_rst_o,
 
        i4_wb_cyc_i,
 
        i4_wb_cyc_i,
 
        i4_wb_stb_i,
 
        i4_wb_stb_i,
 
        i4_wb_adr_i,
 
        i4_wb_adr_i,
 
        i4_wb_sel_i,
 
        i4_wb_sel_i,
 
        i4_wb_we_i,
 
        i4_wb_we_i,
 
        i4_wb_dat_i,
 
        i4_wb_dat_i,
 
        i4_wb_dat_o,
 
        i4_wb_dat_o,
 
        i4_wb_ack_o,
 
        i4_wb_ack_o,
 
        i4_wb_err_o,
 
        i4_wb_err_o,
 
 
 
 
 
 
 
   i5_wb_clk_o,
 
 
 
   i5_wb_rst_o,
 
        i5_wb_cyc_i,
 
        i5_wb_cyc_i,
 
        i5_wb_stb_i,
 
        i5_wb_stb_i,
 
        i5_wb_adr_i,
 
        i5_wb_adr_i,
 
        i5_wb_sel_i,
 
        i5_wb_sel_i,
 
        i5_wb_we_i,
 
        i5_wb_we_i,
 
        i5_wb_dat_i,
 
        i5_wb_dat_i,
 
        i5_wb_dat_o,
 
        i5_wb_dat_o,
 
        i5_wb_ack_o,
 
        i5_wb_ack_o,
 
        i5_wb_err_o,
 
        i5_wb_err_o,
 
 
 
 
 
 
 
   i6_wb_clk_o,
 
 
 
   i6_wb_rst_o,
 
        i6_wb_cyc_i,
 
        i6_wb_cyc_i,
 
        i6_wb_stb_i,
 
        i6_wb_stb_i,
 
        i6_wb_adr_i,
 
        i6_wb_adr_i,
 
        i6_wb_sel_i,
 
        i6_wb_sel_i,
 
        i6_wb_we_i,
 
        i6_wb_we_i,
 
        i6_wb_dat_i,
 
        i6_wb_dat_i,
 
        i6_wb_dat_o,
 
        i6_wb_dat_o,
 
        i6_wb_ack_o,
 
        i6_wb_ack_o,
 
        i6_wb_err_o,
 
        i6_wb_err_o,
 
 
 
 
 
 
 
   i7_wb_clk_o,
 
 
 
   i7_wb_rst_o,
 
        i7_wb_cyc_i,
 
        i7_wb_cyc_i,
 
        i7_wb_stb_i,
 
        i7_wb_stb_i,
 
        i7_wb_adr_i,
 
        i7_wb_adr_i,
 
        i7_wb_sel_i,
 
        i7_wb_sel_i,
 
        i7_wb_we_i,
 
        i7_wb_we_i,
 
        i7_wb_dat_i,
 
        i7_wb_dat_i,
 
        i7_wb_dat_o,
 
        i7_wb_dat_o,
 
        i7_wb_ack_o,
 
        i7_wb_ack_o,
 
        i7_wb_err_o,
 
        i7_wb_err_o,
 
 
 
 
 
 
 
   t0_wb_clk_o,
 
 
 
   t0_wb_rst_o,
 
        t0_wb_cyc_o,
 
        t0_wb_cyc_o,
 
        t0_wb_stb_o,
 
        t0_wb_stb_o,
 
        t0_wb_adr_o,
 
        t0_wb_adr_o,
 
        t0_wb_sel_o,
 
        t0_wb_sel_o,
 
        t0_wb_we_o,
 
        t0_wb_we_o,
 
        t0_wb_dat_o,
 
        t0_wb_dat_o,
 
        t0_wb_dat_i,
 
        t0_wb_dat_i,
 
        t0_wb_ack_i,
 
        t0_wb_ack_i,
 
        t0_wb_err_i,
 
        t0_wb_err_i,
 
 
 
 
 
 
 
   t1_wb_clk_o,
 
 
 
   t1_wb_rst_o,
 
        t1_wb_cyc_o,
 
        t1_wb_cyc_o,
 
        t1_wb_stb_o,
 
        t1_wb_stb_o,
 
        t1_wb_adr_o,
 
        t1_wb_adr_o,
 
        t1_wb_sel_o,
 
        t1_wb_sel_o,
 
        t1_wb_we_o,
 
        t1_wb_we_o,
 
        t1_wb_dat_o,
 
        t1_wb_dat_o,
 
        t1_wb_dat_i,
 
        t1_wb_dat_i,
 
        t1_wb_ack_i,
 
        t1_wb_ack_i,
 
        t1_wb_err_i,
 
        t1_wb_err_i,
 
 
 
 
 
 
 
   t2_wb_clk_o,
 
 
 
   t2_wb_rst_o,
 
        t2_wb_cyc_o,
 
        t2_wb_cyc_o,
 
        t2_wb_stb_o,
 
        t2_wb_stb_o,
 
        t2_wb_adr_o,
 
        t2_wb_adr_o,
 
        t2_wb_sel_o,
 
        t2_wb_sel_o,
 
        t2_wb_we_o,
 
        t2_wb_we_o,
 
        t2_wb_dat_o,
 
        t2_wb_dat_o,
 
        t2_wb_dat_i,
 
        t2_wb_dat_i,
 
        t2_wb_ack_i,
 
        t2_wb_ack_i,
 
        t2_wb_err_i,
 
        t2_wb_err_i,
 
 
 
 
 
 
 
   t3_wb_clk_o,
 
 
 
   t3_wb_rst_o,
 
        t3_wb_cyc_o,
 
        t3_wb_cyc_o,
 
        t3_wb_stb_o,
 
        t3_wb_stb_o,
 
        t3_wb_adr_o,
 
        t3_wb_adr_o,
 
        t3_wb_sel_o,
 
        t3_wb_sel_o,
 
        t3_wb_we_o,
 
        t3_wb_we_o,
 
        t3_wb_dat_o,
 
        t3_wb_dat_o,
 
        t3_wb_dat_i,
 
        t3_wb_dat_i,
 
        t3_wb_ack_i,
 
        t3_wb_ack_i,
 
        t3_wb_err_i,
 
        t3_wb_err_i,
 
 
 
 
 
 
 
   t4_wb_clk_o,
 
 
 
   t4_wb_rst_o,
 
        t4_wb_cyc_o,
 
        t4_wb_cyc_o,
 
        t4_wb_stb_o,
 
        t4_wb_stb_o,
 
        t4_wb_adr_o,
 
        t4_wb_adr_o,
 
        t4_wb_sel_o,
 
        t4_wb_sel_o,
 
        t4_wb_we_o,
 
        t4_wb_we_o,
 
        t4_wb_dat_o,
 
        t4_wb_dat_o,
 
        t4_wb_dat_i,
 
        t4_wb_dat_i,
 
        t4_wb_ack_i,
 
        t4_wb_ack_i,
 
        t4_wb_err_i,
 
        t4_wb_err_i,
 
 
 
 
 
 
 
   t5_wb_clk_o,
 
 
 
   t5_wb_rst_o,
 
        t5_wb_cyc_o,
 
        t5_wb_cyc_o,
 
        t5_wb_stb_o,
 
        t5_wb_stb_o,
 
        t5_wb_adr_o,
 
        t5_wb_adr_o,
 
        t5_wb_sel_o,
 
        t5_wb_sel_o,
 
        t5_wb_we_o,
 
        t5_wb_we_o,
 
        t5_wb_dat_o,
 
        t5_wb_dat_o,
 
        t5_wb_dat_i,
 
        t5_wb_dat_i,
 
        t5_wb_ack_i,
 
        t5_wb_ack_i,
 
        t5_wb_err_i,
 
        t5_wb_err_i,
 
 
 
 
 
 
 
   t6_wb_clk_o,
 
 
 
   t6_wb_rst_o,
 
        t6_wb_cyc_o,
 
        t6_wb_cyc_o,
 
        t6_wb_stb_o,
 
        t6_wb_stb_o,
 
        t6_wb_adr_o,
 
        t6_wb_adr_o,
 
        t6_wb_sel_o,
 
        t6_wb_sel_o,
 
        t6_wb_we_o,
 
        t6_wb_we_o,
 
        t6_wb_dat_o,
 
        t6_wb_dat_o,
 
        t6_wb_dat_i,
 
        t6_wb_dat_i,
 
        t6_wb_ack_i,
 
        t6_wb_ack_i,
 
        t6_wb_err_i,
 
        t6_wb_err_i,
 
 
 
 
 
 
 
   t7_wb_clk_o,
 
 
 
   t7_wb_rst_o,
 
        t7_wb_cyc_o,
 
        t7_wb_cyc_o,
 
        t7_wb_stb_o,
 
        t7_wb_stb_o,
 
        t7_wb_adr_o,
 
        t7_wb_adr_o,
 
        t7_wb_sel_o,
 
        t7_wb_sel_o,
 
        t7_wb_we_o,
 
        t7_wb_we_o,
 
        t7_wb_dat_o,
 
        t7_wb_dat_o,
 
        t7_wb_dat_i,
 
        t7_wb_dat_i,
 
        t7_wb_ack_i,
 
        t7_wb_ack_i,
 
        t7_wb_err_i,
 
        t7_wb_err_i,
 
 
 
 
 
 
 
   t8_wb_clk_o,
 
 
 
   t8_wb_rst_o,
 
        t8_wb_cyc_o,
 
        t8_wb_cyc_o,
 
        t8_wb_stb_o,
 
        t8_wb_stb_o,
 
        t8_wb_adr_o,
 
        t8_wb_adr_o,
 
        t8_wb_sel_o,
 
        t8_wb_sel_o,
 
        t8_wb_we_o,
 
        t8_wb_we_o,
Line 513... Line 547... 
output  [`TC_DW-1:0]     t8_wb_dat_o;
 
output  [`TC_DW-1:0]     t8_wb_dat_o;
 
input   [`TC_DW-1:0]     t8_wb_dat_i;
 
input   [`TC_DW-1:0]     t8_wb_dat_i;
 
input                   t8_wb_ack_i;
 
input                   t8_wb_ack_i;
 
input                   t8_wb_err_i;
 
input                   t8_wb_err_i;
 
 
 
 
 
 
 
 
 
 
 
output i0_wb_clk_o;
 
 
 
output i0_wb_rst_o;
 
 
 
output i1_wb_clk_o;
 
 
 
output i1_wb_rst_o;
 
 
 
output i2_wb_clk_o;
 
 
 
output i2_wb_rst_o;
 
 
 
output i3_wb_clk_o;
 
 
 
output i3_wb_rst_o;
 
 
 
output i4_wb_clk_o;
 
 
 
output i4_wb_rst_o;
 
 
 
output i5_wb_clk_o;
 
 
 
output i5_wb_rst_o;
 
 
 
output i6_wb_clk_o;
 
 
 
output i6_wb_rst_o;
 
 
 
output i7_wb_clk_o;
 
 
 
output i7_wb_rst_o;
 
 
 
output t0_wb_clk_o;
 
 
 
output t0_wb_rst_o;
 
 
 
output t1_wb_clk_o;
 
 
 
output t1_wb_rst_o;
 
 
 
output t2_wb_clk_o;
 
 
 
output t2_wb_rst_o;
 
 
 
output t3_wb_clk_o;
 
 
 
output t3_wb_rst_o;
 
 
 
output t4_wb_clk_o;
 
 
 
output t4_wb_rst_o;
 
 
 
output t5_wb_clk_o;
 
 
 
output t5_wb_rst_o;
 
 
 
output t6_wb_clk_o;
 
 
 
output t6_wb_rst_o;
 
 
 
output t7_wb_clk_o;
 
 
 
output t7_wb_rst_o;
 
 
 
output t8_wb_clk_o;
 
 
 
output t8_wb_rst_o;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
//
 
// Internal wires & registers
 
// Internal wires & registers
 
//
 
//
 
 
 
 
 
//
 
//
Line 583... Line 660... 
wire    [`TC_DW-1:0]     z_wb_dat_i;
 
wire    [`TC_DW-1:0]     z_wb_dat_i;
 
wire    [`TC_DW-1:0]     z_wb_dat_t;
 
wire    [`TC_DW-1:0]     z_wb_dat_t;
 
wire                    z_wb_ack_t;
 
wire                    z_wb_ack_t;
 
wire                    z_wb_err_t;
 
wire                    z_wb_err_t;
 
 
 
 
 
 
 
 
 
 
 
//
 
 
 
// Assign clock and resets
 
 
 
//
 
 
 
assign i0_wb_clk_o = wb_clk_i;
 
 
 
assign i0_wb_rst_o = wb_rst_i;
 
 
 
assign i1_wb_clk_o = wb_clk_i;
 
 
 
assign i1_wb_rst_o = wb_rst_i;
 
 
 
assign i2_wb_clk_o = wb_clk_i;
 
 
 
assign i2_wb_rst_o = wb_rst_i;
 
 
 
assign i3_wb_clk_o = wb_clk_i;
 
 
 
assign i3_wb_rst_o = wb_rst_i;
 
 
 
assign i4_wb_clk_o = wb_clk_i;
 
 
 
assign i4_wb_rst_o = wb_rst_i;
 
 
 
assign i5_wb_clk_o = wb_clk_i;
 
 
 
assign i5_wb_rst_o = wb_rst_i;
 
 
 
assign i6_wb_clk_o = wb_clk_i;
 
 
 
assign i6_wb_rst_o = wb_rst_i;
 
 
 
assign i7_wb_clk_o = wb_clk_i;
 
 
 
assign i7_wb_rst_o = wb_rst_i;
 
 
 
assign t0_wb_clk_o = wb_clk_i;
 
 
 
assign t0_wb_rst_o = wb_rst_i;
 
 
 
assign t1_wb_clk_o = wb_clk_i;
 
 
 
assign t1_wb_rst_o = wb_rst_i;
 
 
 
assign t2_wb_clk_o = wb_clk_i;
 
 
 
assign t2_wb_rst_o = wb_rst_i;
 
 
 
assign t3_wb_clk_o = wb_clk_i;
 
 
 
assign t3_wb_rst_o = wb_rst_i;
 
 
 
assign t4_wb_clk_o = wb_clk_i;
 
 
 
assign t4_wb_rst_o = wb_rst_i;
 
 
 
assign t5_wb_clk_o = wb_clk_i;
 
 
 
assign t5_wb_rst_o = wb_rst_i;
 
 
 
assign t6_wb_clk_o = wb_clk_i;
 
 
 
assign t6_wb_rst_o = wb_rst_i;
 
 
 
assign t7_wb_clk_o = wb_clk_i;
 
 
 
assign t7_wb_rst_o = wb_rst_i;
 
 
 
assign t8_wb_clk_o = wb_clk_i;
 
 
 
assign t8_wb_rst_o = wb_rst_i;
 
 
 
 
 
 
 
 
 
 
 
 
 
//
 
//
 
// Outputs for initiators are ORed from both mi_to_st blocks
 
// Outputs for initiators are ORed from both mi_to_st blocks
 
//
 
//
 
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
 
assign i0_wb_dat_o = xi0_wb_dat_o | yi0_wb_dat_o;
 
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;
 
assign i0_wb_ack_o = xi0_wb_ack_o | yi0_wb_ack_o;

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