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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [wb_connect/] [wb_connect.yaml] - Diff between revs 7 and 10

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Rev 7	Rev 10
Line 1...	Line 1...
`SOCM_CORE`	`SOCM_CORE`
`name: wb_connect`	`name: wb_connect`
`description: A block to connect RISC and peripheral controllers together`	`description: A block to connect RISC and peripheral controllers together`
`version: "1"`	`id: wb_connect,1`
`license: LGPL`	`license: LGPL`
`licensefile:`	`licensefile:`
`author: Damjan Lampret`	`author: Damjan Lampret`
`authormail: lampret@opencores.org`	`authormail: lampret@opencores.org`
`toplevel: minsoc_tc_top`	`toplevel: minsoc_tc_top`
Line 11...	Line 11...


`:clk: SOCM_IFC`	`:clk: SOCM_IFC`
`name: clk`	`name: clk`
`dir: 1`	`dir: 1`
`version: "1"`	`id: clk,1`
`ports:`	`ports:`
`:wb_clk_i: SOCM_PORT`	`:wb_clk_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: clk`	`defn: clk`

`:rst: SOCM_IFC`	`:rst: SOCM_IFC`
`name: rst`	`name: rst`
`dir: 1`	`dir: 1`
`version: "1"`	`id: rst,1`
`ports:`	`ports:`
`:wb_rst_i: SOCM_PORT`	`:wb_rst_i: SOCM_PORT`
`len: 1`	`len: 1`
`defn: rst`	`defn: rst`



`:i0: SOCM_IFC`	`:i0: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i0_wb_clk_o: SOCM_PORT`	`:i0_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i0_wb_rst_o: SOCM_PORT`	`:i0_wb_rst_o: SOCM_PORT`
Line 69...	Line 69...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i1: SOCM_IFC`	`:i1: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i1_wb_clk_o: SOCM_PORT`	`:i1_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i1_wb_rst_o: SOCM_PORT`	`:i1_wb_rst_o: SOCM_PORT`
Line 107...	Line 107...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i2: SOCM_IFC`	`:i2: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i2_wb_clk_o: SOCM_PORT`	`:i2_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i2_wb_rst_o: SOCM_PORT`	`:i2_wb_rst_o: SOCM_PORT`
Line 145...	Line 145...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i3: SOCM_IFC`	`:i3: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i3_wb_clk_o: SOCM_PORT`	`:i3_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i3_wb_rst_o: SOCM_PORT`	`:i3_wb_rst_o: SOCM_PORT`
Line 183...	Line 183...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i4: SOCM_IFC`	`:i4: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i4_wb_clk_o: SOCM_PORT`	`:i4_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i4_wb_rst_o: SOCM_PORT`	`:i4_wb_rst_o: SOCM_PORT`
Line 221...	Line 221...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i5: SOCM_IFC`	`:i5: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i5_wb_clk_o: SOCM_PORT`	`:i5_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i5_wb_rst_o: SOCM_PORT`	`:i5_wb_rst_o: SOCM_PORT`
Line 259...	Line 259...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i6: SOCM_IFC`	`:i6: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i6_wb_clk_o: SOCM_PORT`	`:i6_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i6_wb_rst_o: SOCM_PORT`	`:i6_wb_rst_o: SOCM_PORT`
Line 297...	Line 297...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:i7: SOCM_IFC`	`:i7: SOCM_IFC`
`name: wishbone_ma`	`name: wishbone_ma`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_ma,b3`
`ports:`	`ports:`
`:i7_wb_clk_o: SOCM_PORT`	`:i7_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:i7_wb_rst_o: SOCM_PORT`	`:i7_wb_rst_o: SOCM_PORT`
Line 335...	Line 335...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t0: SOCM_IFC`	`:t0: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t0_wb_clk_o: SOCM_PORT`	`:t0_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t0_wb_rst_o: SOCM_PORT`	`:t0_wb_rst_o: SOCM_PORT`
Line 373...	Line 373...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t1: SOCM_IFC`	`:t1: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t1_wb_clk_o: SOCM_PORT`	`:t1_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t1_wb_rst_o: SOCM_PORT`	`:t1_wb_rst_o: SOCM_PORT`
Line 411...	Line 411...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t2: SOCM_IFC`	`:t2: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t2_wb_clk_o: SOCM_PORT`	`:t2_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t2_wb_rst_o: SOCM_PORT`	`:t2_wb_rst_o: SOCM_PORT`
Line 449...	Line 449...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t3: SOCM_IFC`	`:t3: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t3_wb_clk_o: SOCM_PORT`	`:t3_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t3_wb_rst_o: SOCM_PORT`	`:t3_wb_rst_o: SOCM_PORT`
Line 487...	Line 487...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t4: SOCM_IFC`	`:t4: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t4_wb_clk_o: SOCM_PORT`	`:t4_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t4_wb_rst_o: SOCM_PORT`	`:t4_wb_rst_o: SOCM_PORT`
Line 525...	Line 525...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t5: SOCM_IFC`	`:t5: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t5_wb_clk_o: SOCM_PORT`	`:t5_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t5_wb_rst_o: SOCM_PORT`	`:t5_wb_rst_o: SOCM_PORT`
Line 563...	Line 563...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t6: SOCM_IFC`	`:t6: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t6_wb_clk_o: SOCM_PORT`	`:t6_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t6_wb_rst_o: SOCM_PORT`	`:t6_wb_rst_o: SOCM_PORT`
Line 601...	Line 601...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t7: SOCM_IFC`	`:t7: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t7_wb_clk_o: SOCM_PORT`	`:t7_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t7_wb_rst_o: SOCM_PORT`	`:t7_wb_rst_o: SOCM_PORT`
Line 639...	Line 639...
`defn: err`	`defn: err`
`len: 1`	`len: 1`
`:t8: SOCM_IFC`	`:t8: SOCM_IFC`
`name: wishbone_sl`	`name: wishbone_sl`
`dir: 0`	`dir: 0`
`version: "b3"`	`id: wishbone_sl,b3`
`ports:`	`ports:`
`:t8_wb_clk_o: SOCM_PORT`	`:t8_wb_clk_o: SOCM_PORT`
`defn: clk`	`defn: clk`
`len: 1`	`len: 1`
`:t8_wb_rst_o: SOCM_PORT`	`:t8_wb_rst_o: SOCM_PORT`

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[/] [soc_maker/] [trunk/] [core_lib/] [cores/] [wb_connect/] [wb_connect.yaml] - Diff between revs 7 and 10