--
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--
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-- Front-end for SpaceWire Receiver
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-- Front-end for SpaceWire Receiver
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--
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--
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-- This entity samples the input signals DataIn and StrobeIn to detect
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-- This entity samples the input signals DataIn and StrobeIn to detect
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-- valid bit transitions. Received bits are handed to the application.
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-- valid bit transitions. Received bits are handed to the application.
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--
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--
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-- Inputs are sampled on the rising edge of the system clock, therefore
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-- Inputs are sampled on the rising edge of the system clock, therefore
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-- the maximum bitrate of the incoming signal must be significantly lower
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-- the maximum bitrate of the incoming signal must be significantly lower
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-- than system clock frequency.
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-- than system clock frequency.
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--
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--
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.numeric_std.all;
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entity spwrecvfront_generic is
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entity spwrecvfront_generic is
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port (
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port (
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-- System clock.
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-- System clock.
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clk: in std_logic;
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clk: in std_logic;
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-- High to enable receiver; low to disable and reset receiver.
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-- High to enable receiver; low to disable and reset receiver.
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rxen: in std_logic;
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rxen: in std_logic;
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-- High if there has been recent activity on the input lines.
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-- High if there has been recent activity on the input lines.
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inact: out std_logic;
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inact: out std_logic;
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-- High if inbits contains a valid received bit.
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-- High if inbits contains a valid received bit.
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-- If inbvalid='1', the application must sample inbits on
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-- If inbvalid='1', the application must sample inbits on
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-- the rising edge of clk.
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-- the rising edge of clk.
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inbvalid: out std_logic;
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inbvalid: out std_logic;
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-- Received bit
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-- Received bit
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inbits: out std_logic_vector(0 downto 0);
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inbits: out std_logic_vector(0 downto 0);
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|
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-- Data In signal from SpaceWire bus.
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-- Data In signal from SpaceWire bus.
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spw_di: in std_logic;
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spw_di: in std_logic;
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-- Strobe In signal from SpaceWire bus.
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-- Strobe In signal from SpaceWire bus.
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spw_si: in std_logic );
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spw_si: in std_logic );
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end entity spwrecvfront_generic;
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end entity spwrecvfront_generic;
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architecture spwrecvfront_arch of spwrecvfront_generic is
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architecture spwrecvfront_arch of spwrecvfront_generic is
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|
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-- input flip-flops
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-- input flip-flops
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signal s_spwdi1: std_ulogic;
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signal s_spwdi1: std_ulogic;
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signal s_spwsi1: std_ulogic;
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signal s_spwsi1: std_ulogic;
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signal s_spwdi2: std_ulogic;
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signal s_spwdi2: std_ulogic;
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signal s_spwsi2: std_ulogic;
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signal s_spwsi2: std_ulogic;
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|
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-- data/strobe decoding
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-- data/strobe decoding
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signal s_spwsi3: std_ulogic;
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signal s_spwsi3: std_ulogic;
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|
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-- output registers
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-- output registers
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signal s_inbvalid: std_ulogic;
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signal s_inbvalid: std_ulogic;
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signal s_inbit: std_ulogic;
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signal s_inbit: std_ulogic;
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|
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begin
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begin
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-- drive outputs
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-- drive outputs
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inact <= s_inbvalid;
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inact <= s_inbvalid;
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inbvalid <= s_inbvalid;
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inbvalid <= s_inbvalid;
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inbits(0) <= s_inbit;
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inbits(0) <= s_inbit;
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|
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-- synchronous process
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-- synchronous process
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process (clk) is
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process (clk) is
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begin
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begin
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if rising_edge(clk) then
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if rising_edge(clk) then
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|
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-- sample input signal
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-- sample input signal
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s_spwdi1 <= spw_di;
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s_spwdi1 <= spw_di;
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s_spwsi1 <= spw_si;
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s_spwsi1 <= spw_si;
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|
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-- more flip-flops for safe synchronization
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-- more flip-flops for safe synchronization
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s_spwdi2 <= s_spwdi1;
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s_spwdi2 <= s_spwdi1;
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s_spwsi2 <= s_spwsi1;
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s_spwsi2 <= s_spwsi1;
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|
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-- keep strobe signal for data/strobe decoding
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-- keep strobe signal for data/strobe decoding
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s_spwsi3 <= s_spwsi2;
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s_spwsi3 <= s_spwsi2;
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|
|
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-- keep data bit for data/strobe decoding
|
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s_inbit <= s_spwdi2;
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|
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if rxen = '1' then
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if rxen = '1' then
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-- data/strobe decoding
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-- data/strobe decoding
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s_inbit <= s_spwdi2;
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s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3;
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s_inbvalid <= s_spwdi2 xor s_spwsi2 xor s_inbit xor s_spwsi3;
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else
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else
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-- reset receiver
|
-- reset receiver
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s_inbit <= '0';
|
|
s_inbvalid <= '0';
|
s_inbvalid <= '0';
|
end if;
|
end if;
|
|
|
end if;
|
end if;
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end process;
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end process;
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|
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end architecture spwrecvfront_arch;
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end architecture spwrecvfront_arch;
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