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use gaisler.can.all;
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use gaisler.can.all;
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use gaisler.net.all;
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use gaisler.net.all;
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use gaisler.jtag.all;
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use gaisler.jtag.all;
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use gaisler.spacewire.all;
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use gaisler.spacewire.all;
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use gaisler.grusb.all;
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use gaisler.grusb.all;
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use gaisler.ata.all;
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library esa;
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library esa;
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use esa.memoryctrl.all;
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use esa.memoryctrl.all;
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library unisim;
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library unisim;
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usb_termsel : out std_ulogic;
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usb_termsel : out std_ulogic;
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usb_txready : in std_ulogic;
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usb_txready : in std_ulogic;
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usb_txvalid : out std_ulogic;
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usb_txvalid : out std_ulogic;
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usb_validh : inout std_ulogic;
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usb_validh : inout std_ulogic;
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usb_xcvrsel : out std_ulogic;
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usb_xcvrsel : out std_ulogic;
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usb_vbus : in std_ulogic;
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usb_vbus : in std_ulogic
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ata_rstn : out std_logic;
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ata_data : inout std_logic_vector(15 downto 0);
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ata_da : out std_logic_vector(2 downto 0);
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ata_cs0 : out std_logic;
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ata_cs1 : out std_logic;
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ata_dior : out std_logic;
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ata_diow : out std_logic;
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ata_iordy : in std_logic;
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ata_intrq : in std_logic;
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ata_dmarq : in std_logic;
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ata_dmack : out std_logic;
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--ata_dasp : in std_logic
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ata_csel : out std_logic
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);
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);
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end;
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end;
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architecture rtl of leon3mp is
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
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constant maxahbm : integer := CFG_NCPU+CFG_AHB_UART+CFG_GRETH+
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CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
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CFG_AHB_JTAG+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+CFG_SVGA_ENABLE+
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CFG_ATA+CFG_GRUSBDC;
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CFG_GRUSBDC;
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal wpo : wprot_out_type;
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signal mouo : ps2_out_type;
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signal mouo : ps2_out_type;
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signal vgao : apbvga_out_type;
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signal vgao : apbvga_out_type;
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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constant IOAEN : integer := CFG_CAN + CFG_ATA + CFG_GRUSBDC;
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constant IOAEN : integer := CFG_CAN + CFG_GRUSBDC;
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signal stati : ahbstat_in_type;
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signal stati : ahbstat_in_type;
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signal spw_clkl : std_ulogic;
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signal spw_clkl : std_ulogic;
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signal spw_tick_in: std_logic;
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signal spw_tick_in: std_logic;
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signal uclk : std_ulogic;
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signal uclk : std_ulogic;
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signal usbi : grusb_in_type;
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signal usbi : grusb_in_type;
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signal usbo : grusb_out_type;
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signal usbo : grusb_out_type;
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signal idei : ata_in_type;
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signal ideo : ata_out_type;
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constant SPW_LOOP_BACK : integer := 0;
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constant SPW_LOOP_BACK : integer := 0;
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signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
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signal dac_clk, video_clk, clk50 : std_logic; -- signals to vga_clkgen.
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signal clk_sel : std_logic_vector(1 downto 0);
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signal clk_sel : std_logic_vector(1 downto 0);
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Line 803... |
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
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ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE+
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CFG_SPW_NUM*CFG_SPW_EN));
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CFG_SPW_NUM*CFG_SPW_EN));
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end generate usb_dcl0;
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end generate usb_dcl0;
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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--- AHB ATA ----------------------------------------------------------
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-----------------------------------------------------------------------
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ata0 : if CFG_ATA = 1 generate
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atac0 : atactrl
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generic map(
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tech => 0, fdepth => CFG_ATAFIFO,
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mhindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
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CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+CFG_GRUSB_DCL+
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CFG_GRUSBDC,
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shindex => 3, haddr => 16#A00#, hmask => 16#fff#, pirq => CFG_ATAIRQ,
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mwdma => CFG_ATADMA, TWIDTH => 8,
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-- PIO mode 0 settings (@100MHz clock)
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PIO_mode0_T1 => 6, -- 70ns
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PIO_mode0_T2 => 28, -- 290ns
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PIO_mode0_T4 => 2, -- 30ns
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PIO_mode0_Teoc => 23 -- 240ns ==> T0 - T1 - T2 = 600 - 70 - 290 = 240
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)
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port map(
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rst => rstn, arst => vcc(0), clk => clkm, ahbmi => ahbmi,
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ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG+
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CFG_SVGA_ENABLE+CFG_SPW_NUM*CFG_SPW_EN+
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CFG_GRUSB_DCL+CFG_GRUSBDC),
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ahbsi => ahbsi, ahbso => ahbso(3), atai => idei, atao => ideo);
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ata_rstn_pad : outpad generic map (tech => padtech)
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port map (ata_rstn, ideo.rstn);
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ata_data_pad : iopadv generic map (tech => padtech, width => 16, oepol => 1)
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port map (ata_data, ideo.ddo, ideo.oen, idei.ddi);
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ata_da_pad : outpadv generic map (tech => padtech, width => 3)
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port map (ata_da, ideo.da);
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ata_cs0_pad : outpad generic map (tech => padtech)
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port map (ata_cs0, ideo.cs0);
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ata_cs1_pad : outpad generic map (tech => padtech)
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port map (ata_cs1, ideo.cs1);
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ata_dior_pad : outpad generic map (tech => padtech)
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port map (ata_dior, ideo.dior);
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ata_diow_pad : outpad generic map (tech => padtech)
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port map (ata_diow, ideo.diow);
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iordy_pad : inpad generic map (tech => padtech)
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port map (ata_iordy, idei.iordy);
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intrq_pad : inpad generic map (tech => padtech)
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port map (ata_intrq, idei.intrq);
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dmarq_pad : inpad generic map (tech => padtech)
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port map (ata_dmarq, idei.dmarq);
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dmack_pad : outpad generic map (tech => padtech)
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port map (ata_dmack, ideo.dmack);
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ata_csel <= '0';
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end generate;
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-----------------------------------------------------------------------
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--- Drive unused bus elements ---------------------------------------
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--- Drive unused bus elements ---------------------------------------
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-----------------------------------------------------------------------
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-----------------------------------------------------------------------
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-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
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-- nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
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-- ahbmo(i) <= ahbm_none;
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-- ahbmo(i) <= ahbm_none;
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