URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [streamtest_digilent-xc3s200/] [streamtest.ucf] - Diff between revs 6 and 7

Rev 6	Rev 7
Line 3...	Line 3...
`# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns`	`# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns`
`NET "clk50" TNM_NET = "clk50" ;`	`NET "clk50" TNM_NET = "clk50" ;`
`TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;`	`TIMESPEC "TS_clk" = PERIOD "clk50" 18.0 ns ;`

`# Paths between fastclk and sysclk must be constrained to fastclk period.`	`# Paths between fastclk and sysclk must be constrained to fastclk period.`
`# fastclk = 200 MHz = 5 ns = 3 ns delay + 2 ns skew`	`# fastclk = 200 MHz = 5 ns = 4 ns delay + 1 ns margin`
`NET "sysclk" TNM_NET = "sysclk" \| MAXSKEW = 1 ns;`	`NET "sysclk" TNM_NET = "sysclk" ;`
`NET "fastclk" TNM_NET = "fastclk" \| MAXSKEW = 1 ns;`	`NET "fastclk" TNM_NET = "fastclk" ;`
`TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;`	`TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;`
`TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;`	`TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;`
	`TIMESPEC "TS_sync" = FROM FFS("/syncdff_ff1") TO FFS("/syncdff_ff2") 2 ns ;`

`NET "clk50" LOC = "T9" ;`	`NET "clk50" LOC = "T9" ;`
`NET "led(0)" LOC = "K12" \| DRIVE = 6 ;`	`NET "led(0)" LOC = "K12" \| DRIVE = 6 ;`
`NET "led(1)" LOC = "P14" \| DRIVE = 6 ;`	`NET "led(1)" LOC = "P14" \| DRIVE = 6 ;`
`NET "led(2)" LOC = "L12" \| DRIVE = 6 ;`	`NET "led(2)" LOC = "L12" \| DRIVE = 6 ;`