URL https://opencores.org/ocsvn/spacewire_light/spacewire_light/trunk

Subversion Repositories spacewire_light

[/] [spacewire_light/] [trunk/] [syn/] [streamtest_gr-xc3s1500/] [streamtest.ucf] - Diff between revs 5 and 7

Rev 5	Rev 7
Line 3...	Line 3...
`# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns`	`# Board clock, 50 MHz = 20 ns nominal, - 2 ns margin = 18 ns`
`NET "clk" TNM_NET = "clk" ;`	`NET "clk" TNM_NET = "clk" ;`
`TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;`	`TIMESPEC "TS_clk" = PERIOD "clk" 18.0 ns ;`

`# Paths between fastclk and sysclk must be constrained to fastclk period.`	`# Paths between fastclk and sysclk must be constrained to fastclk period.`
`# fastclk = 200 MHz = 5 ns nominal`	`# fastclk = 200 MHz = 5 ns nominal = 4 ns data path + 1 ns margin`
`# 3 ns data path + 1 ns source skew + 1 ns destination skew = 5 ns`
`NET "sysclk" TNM_NET = "sysclk" ;`	`NET "sysclk" TNM_NET = "sysclk" ;`
`NET "fastclk" TNM_NET = "fastclk" ;`	`NET "fastclk" TNM_NET = "fastclk" ;`
`TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 3 ns DATAPATHONLY ;`	`TIMESPEC "TS_fast_to_sys" = FROM "fastclk" TO "sysclk" 4 ns DATAPATHONLY ;`
`TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 3 ns DATAPATHONLY ;`	`TIMESPEC "TS_sys_to_fast" = FROM "sysclk" TO "fastclk" 4 ns DATAPATHONLY ;`
`NET "sysclk" MAXSKEW = 1 ns ;`	`TIMESPEC "TS_sync" = FROM FFS("/syncdff_ff1") TO FFS("/syncdff_ff2") 2 ns ;`
`NET "fastclk" MAXSKEW = 1 ns ;`

`# Board clock`	`# Board clock`
`NET "clk" LOC = "aa12" \| IOSTANDARD = LVTTL;`	`NET "clk" LOC = "aa12" \| IOSTANDARD = LVTTL;`

`# Note: LEDs use inverted logic`	`# Note: LEDs use inverted logic`