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Flow report for spw_fifo_ulight
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Flow report for spw_fifo_ulight
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Fri Sep 15 08:19:20 2017
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Mon Feb 5 00:59:12 2018
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Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
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Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
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---------------------
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---------------------
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; Table of Contents ;
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; Table of Contents ;
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---------------------
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---------------------
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functions, and any output files from any of the foregoing
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel MegaCore Function License Agreement, or other
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the Intel FPGA IP License Agreement, or other applicable license
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applicable license agreement, including, without limitation,
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agreement, including, without limitation, that your use is for
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that your use is for the sole purpose of programming logic
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the sole purpose of programming logic devices manufactured by
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devices manufactured by Intel and sold by Intel or its
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Intel and sold by Intel or its authorized distributors. Please
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authorized distributors. Please refer to the applicable
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refer to the applicable agreement for further details.
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agreement for further details.
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+-------------------------------------------------------------------------------+
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+----------------------------------------------------------------------------------------+
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; Flow Summary ;
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; Flow Summary ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+------------------------------------------------------+
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; Flow Status ; Successful - Fri Sep 15 08:19:20 2017 ;
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; Flow Status ; Successful - Mon Feb 5 00:59:12 2018 ;
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; Quartus Prime Version ; 17.0.1 Build 598 06/07/2017 SJ Lite Edition ;
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; Quartus Prime Version ; 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition ;
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; Revision Name ; spw_fifo_ulight ;
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; Revision Name ; spw_fifo_ulight ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Top-level Entity Name ; SPW_ULIGHT_FIFO ;
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; Family ; Cyclone V ;
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; Family ; Cyclone V ;
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; Device ; 5CSEMA4U23C6 ;
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; Device ; 5CSEMA4U23C6 ;
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; Timing Models ; Final ;
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; Timing Models ; Final ;
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; Logic utilization (in ALMs) ; 3,209 / 15,880 ( 20 % ) ;
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; Logic utilization (in ALMs) ; 3,362 / 15,880 ( 21 % ) ;
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; Total registers ; 4692 ;
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; Total registers ; 4633 ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total pins ; 19 / 314 ( 6 % ) ;
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; Total virtual pins ; 0 ;
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; Total virtual pins ; 0 ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total block memory bits ; 0 / 2,764,800 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total DSP Blocks ; 0 / 84 ( 0 % ) ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI RX PCSs ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI PMA RX Deserializers ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI TX PCSs ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total HSSI PMA TX Serializers ; 0 ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total PLLs ; 1 / 5 ( 20 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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; Total DLLs ; 0 / 4 ( 0 % ) ;
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+---------------------------------+---------------------------------------------+
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+---------------------------------+------------------------------------------------------+
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+-----------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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; Flow Settings ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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; Option ; Setting ;
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; Option ; Setting ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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; Start date & time ; 09/15/2017 08:07:49 ;
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; Start date & time ; 02/05/2018 00:47:03 ;
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; Main task ; Compilation ;
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; Main task ; Compilation ;
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; Revision Name ; spw_fifo_ulight ;
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; Revision Name ; spw_fifo_ulight ;
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+-------------------+---------------------+
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+-------------------+---------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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; Flow Non-Default Global Settings ;
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+
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; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_DUPLICATION ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_MERGING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
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; ALLOW_REGISTER_RETIMING ; Off ; On ; -- ; -- ;
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; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
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; ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
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; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
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; ALLOW_SYNCH_CTRL_USAGE ; Off ; On ; -- ; -- ;
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; AUTO_DELAY_CHAINS ; Off ; On ; -- ; -- ;
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; ALM_REGISTER_PACKING_EFFORT ; High ; Medium ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 31032335263289.150547366508423 ; -- ; -- ; -- ;
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; AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ; On ; Off ; -- ; -- ;
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; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
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; AUTO_DSP_RECOGNITION ; Off ; On ; -- ; -- ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ;
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; AUTO_RAM_RECOGNITION ; Off ; On ; -- ; -- ;
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; AUTO_ROM_RECOGNITION ; Off ; On ; -- ; -- ;
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; AUTO_SHIFT_REGISTER_RECOGNITION ; Off ; Auto ; -- ; -- ;
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; BLOCK_RAM_TO_MLAB_CELL_CONVERSION ; Off ; On ; -- ; -- ;
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; COMPILER_SIGNATURE_ID ; 31032335263289.151779881804543 ; -- ; -- ; -- ;
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; DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES ; Off ; Auto ; -- ; -- ;
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; EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ; HSPICE (Signal Integrity) ; ; -- ; -- ;
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; EDA_BOARD_DESIGN_TIMING_TOOL ; Stamp (Timing) ; ; -- ; -- ;
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; EDA_INPUT_DATA_FORMAT ; Edif ; -- ; -- ; eda_design_synthesis ;
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; EDA_OUTPUT_DATA_FORMAT ; Stamp ; -- ; -- ; eda_board_design_timing ;
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; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_simulation ;
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; EDA_OUTPUT_DATA_FORMAT ; Hspice ; -- ; -- ; eda_board_design_signal_integrity ;
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; EDA_OUTPUT_DATA_FORMAT ; None ; -- ; -- ; eda_board_design_symbol ;
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; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_simulation ;
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; EDA_RUN_TOOL_AUTOMATICALLY ; Off ; -- ; -- ; eda_design_synthesis ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; ENABLE_SIGNALTAP ; Off ; -- ; -- ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sdram_io.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/alt_types.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/system.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.c ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; HPS_ISW_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer.pre.h ; -- ; ulight_fifo_hps_0_hps_io_border ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_ac_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto_inst_init.pre.c ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/sequencer_auto.pre.h ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/sequencer/emif.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;
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; MISC_FILE ; ulight_fifo/synthesis/submodules/hps.pre.xml ; -- ; -- ; -- ;
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; OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ;
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; MUX_RESTRUCTURE ; Off ; Auto ; -- ; -- ;
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; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Off ; Normal ; -- ; -- ;
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; OPTIMIZATION_MODE ; High Performance Effort ; Balanced ; -- ; -- ;
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; OPTIMIZE_FOR_METASTABILITY ; Off ; On ; -- ; -- ;
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; OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING ; Pack All IO Registers ; Normal ; -- ; -- ;
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; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
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; OPTIMIZE_POWER_DURING_FITTING ; Extra effort ; Normal compilation ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; SPW_ULIGHT_FIFO ; Top ;
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; PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ; On ; Off ; -- ; -- ;
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; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ;
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; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ;
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; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
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; PHYSICAL_SYNTHESIS_EFFORT ; Extra ; Normal ; -- ; -- ;
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; PLACEMENT_EFFORT_MULTIPLIER ; 90.0 ; 1.0 ; -- ; -- ;
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; PLACEMENT_EFFORT_MULTIPLIER ; 4.0 ; 1.0 ; -- ; -- ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
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; REMOVE_DUPLICATE_REGISTERS ; Off ; On ; -- ; -- ;
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; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_REGISTER_DUPLICATION ; Off ; Auto ; -- ; -- ;
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; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
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; ROUTER_TIMING_OPTIMIZATION_LEVEL ; MAXIMUM ; Normal ; -- ; -- ;
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; SEED ; 893763639 ; 1 ; -- ; -- ;
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; SAFE_STATE_MACHINE ; On ; Off ; -- ; -- ;
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; SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL ; Off ; On ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.regmap ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
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; SLD_FILE ; ulight_fifo/synthesis/ulight_fifo.debuginfo ; -- ; -- ; -- ;
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; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1502975928 ; -- ; ulight_fifo ; -- ;
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; SLD_INFO ; QSYS_NAME ulight_fifo HAS_SOPCINFO 1 GENERATION_ID 1516735843 ; -- ; ulight_fifo ; -- ;
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; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
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; SOPCINFO_FILE ; ulight_fifo/synthesis/../../ulight_fifo.sopcinfo ; -- ; -- ; -- ;
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; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
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; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ;
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; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
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; SYNTHESIS_ONLY_QIP ; On ; -- ; -- ; -- ;
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; SYNTH_GATED_CLOCK_CONVERSION ; On ; Off ; -- ; -- ;
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; SYNTH_PROTECT_SDC_CONSTRAINT ; On ; Off ; -- ; -- ;
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; SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM ; Off ; On ; -- ; -- ;
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; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;
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; TOP_LEVEL_ENTITY ; SPW_ULIGHT_FIFO ; spw_fifo_ulight ; -- ; -- ;
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+-------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+----------------+
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; USE_SIGNALTAP_FILE ; output_files/stp2.stp ; -- ; -- ; -- ;
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+---------------------------------------------------+---------------------------------------------------------------------------+--------------------+---------------------------------+-----------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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+-------------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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; Flow Elapsed Time ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:01:16 ; 1.3 ; 1339 MB ; 00:01:53 ;
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; Analysis & Synthesis ; 00:01:23 ; 1.3 ; 1287 MB ; 00:01:52 ;
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; Fitter ; 00:04:42 ; 1.0 ; 2064 MB ; 00:08:17 ;
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; Fitter ; 00:05:06 ; 1.1 ; 2473 MB ; 00:08:48 ;
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; Assembler ; 00:00:18 ; 1.0 ; 1040 MB ; 00:00:12 ;
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; Assembler ; 00:00:19 ; 1.0 ; 1044 MB ; 00:00:11 ;
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; TimeQuest Timing Analyzer ; 00:00:54 ; 1.5 ; 1351 MB ; 00:01:15 ;
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; TimeQuest Timing Analyzer ; 00:01:19 ; 1.2 ; 1444 MB ; 00:01:24 ;
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; EDA Netlist Writer ; 00:00:08 ; 1.0 ; 1314 MB ; 00:00:08 ;
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; EDA Netlist Writer ; 00:00:06 ; 1.0 ; 1244 MB ; 00:00:06 ;
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; Total ; 00:07:18 ; -- ; -- ; 00:11:45 ;
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; Total ; 00:08:13 ; -- ; -- ; 00:12:21 ;
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
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+-----------------------------------------------------------------------------------------+
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+-----------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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; Flow OS Summary ;
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