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[/] [spacewiresystemc/] [trunk/] [altera_work/] [spw_fifo_ulight/] [output_files/] [spw_fifo_ulight.map.summary] - Diff between revs 35 and 40

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Rev 35 Rev 40
Line 1... Line 1...
Analysis & Synthesis Status : Successful - Fri Sep 15 08:13:05 2017
Analysis & Synthesis Status : Successful - Mon Feb  5 00:52:09 2018
Quartus Prime Version : 17.0.1 Build 598 06/07/2017 SJ Lite Edition
Quartus Prime Version : 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
Revision Name : spw_fifo_ulight
Revision Name : spw_fifo_ulight
Top-level Entity Name : SPW_ULIGHT_FIFO
Top-level Entity Name : SPW_ULIGHT_FIFO
Family : Cyclone V
Family : Cyclone V
Logic utilization (in ALMs) : N/A
Logic utilization (in ALMs) : N/A
Total registers : 4692
Total registers : 4628
Total pins : 15
Total pins : 15
Total virtual pins : 0
Total virtual pins : 0
Total block memory bits : 0
Total block memory bits : 0
Total DSP Blocks : 0
Total DSP Blocks : 0
Total HSSI RX PCSs : 0
Total HSSI RX PCSs : 0

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