| Line 4... |
Line 4... |
-- functions, and any output files from any of the foregoing
|
-- functions, and any output files from any of the foregoing
|
-- (including device programming or simulation files), and any
|
-- (including device programming or simulation files), and any
|
-- associated documentation or information are expressly subject
|
-- associated documentation or information are expressly subject
|
-- to the terms and conditions of the Intel Program License
|
-- to the terms and conditions of the Intel Program License
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
-- Subscription Agreement, the Intel Quartus Prime License Agreement,
|
-- the Intel MegaCore Function License Agreement, or other
|
-- the Intel FPGA IP License Agreement, or other applicable license
|
-- applicable license agreement, including, without limitation,
|
-- agreement, including, without limitation, that your use is for
|
-- that your use is for the sole purpose of programming logic
|
-- the sole purpose of programming logic devices manufactured by
|
-- devices manufactured by Intel and sold by Intel or its
|
-- Intel and sold by Intel or its authorized distributors. Please
|
-- authorized distributors. Please refer to the applicable
|
-- refer to the applicable agreement for further details.
|
-- agreement for further details.
|
|
--
|
--
|
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
|
-- This is a Quartus Prime output file. It is for reporting purposes only, and is
|
-- not intended for use as a Quartus Prime input file. This file cannot be used
|
-- not intended for use as a Quartus Prime input file. This file cannot be used
|
-- to make Quartus Prime pin assignments - for instructions on how to make pin
|
-- to make Quartus Prime pin assignments - for instructions on how to make pin
|
-- assignments, please see Quartus Prime help.
|
-- assignments, please see Quartus Prime help.
|
| Line 71... |
Line 70... |
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---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
-- Pin directions (input, output or bidir) are based on device operating in user mode.
|
---------------------------------------------------------------------------------
|
---------------------------------------------------------------------------------
|
|
|
Quartus Prime Version 17.0.1 Build 598 06/07/2017 SJ Lite Edition
|
Quartus Prime Version 17.1.1 Internal Build 593 12/11/2017 SJ Lite Edition
|
CHIP "spw_fifo_ulight" ASSIGNED TO AN: 5CSEMA4U23C6
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CHIP "spw_fifo_ulight" ASSIGNED TO AN: 5CSEMA4U23C6
|
|
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
|
-------------------------------------------------------------------------------------------------------------
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-------------------------------------------------------------------------------------------------------------
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DNU : A2 : : : : :
|
DNU : A2 : : : : :
|
