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//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
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//altiobuf_out CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=1 OPEN_DRAIN_OUTPUT="FALSE" PSEUDO_DIFFERENTIAL_MODE="TRUE" USE_DIFFERENTIAL_MODE="TRUE" USE_OE="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN1="FALSE" USE_OUT_DYNAMIC_DELAY_CHAIN2="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataout dataout_b
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//VERSION_BEGIN 17.0 cbx_altiobuf_out 2017:06:01:09:22:16:SJ cbx_mgl 2017:06:01:10:52:00:SJ cbx_stratixiii 2017:06:01:09:22:16:SJ cbx_stratixv 2017:06:01:09:22:16:SJ VERSION_END
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//VERSION_BEGIN 17.1 cbx_altiobuf_out 2017:12:05:11:11:27:SJ cbx_mgl 2017:12:05:12:41:31:SJ cbx_stratixiii 2017:12:05:11:11:27:SJ cbx_stratixv 2017:12:05:11:11:27:SJ VERSION_END
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// synthesis VERILOG_INPUT_VERSION VERILOG_2001
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// altera message_off 10463
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// altera message_off 10463
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// functions, and any output files from any of the foregoing
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// functions, and any output files from any of the foregoing
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// (including device programming or simulation files), and any
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// (including device programming or simulation files), and any
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// associated documentation or information are expressly subject
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// associated documentation or information are expressly subject
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// to the terms and conditions of the Intel Program License
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// to the terms and conditions of the Intel Program License
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// Subscription Agreement, the Intel Quartus Prime License Agreement,
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// the Intel MegaCore Function License Agreement, or other
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// the Intel FPGA IP License Agreement, or other applicable license
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// applicable license agreement, including, without limitation,
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// agreement, including, without limitation, that your use is for
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// that your use is for the sole purpose of programming logic
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// the sole purpose of programming logic devices manufactured by
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// devices manufactured by Intel and sold by Intel or its
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// Intel and sold by Intel or its authorized distributors. Please
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// authorized distributors. Please refer to the applicable
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// refer to the applicable agreement for further details.
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// agreement for further details.
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//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
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//synthesis_resources = cyclonev_io_obuf 2 cyclonev_pseudo_diff_out 1
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//synopsys translate_off
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//synopsys translate_off
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