//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
|
//use of Altera Corporation's design tools, logic functions and other
|
//use of Altera Corporation's design tools, logic functions and other
|
//software and tools, and its AMPP partner logic functions, and any
|
//software and tools, and its AMPP partner logic functions, and any
|
//output files any of the foregoing (including device programming or
|
//output files any of the foregoing (including device programming or
|
//simulation files), and any associated documentation or information are
|
//simulation files), and any associated documentation or information are
|
//expressly subject to the terms and conditions of the Altera Program
|
//expressly subject to the terms and conditions of the Altera Program
|
//License Subscription Agreement or other applicable license agreement,
|
//License Subscription Agreement or other applicable license agreement,
|
//including, without limitation, that your use is for the sole purpose
|
//including, without limitation, that your use is for the sole purpose
|
//of programming logic devices manufactured by Altera and sold by Altera
|
//of programming logic devices manufactured by Altera and sold by Altera
|
//or its authorized distributors. Please refer to the applicable
|
//or its authorized distributors. Please refer to the applicable
|
//agreement for further details.
|
//agreement for further details.
|
|
|
// synthesis translate_off
|
// synthesis translate_off
|
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
// synthesis translate_on
|
// synthesis translate_on
|
|
|
// turn off superfluous verilog processor warnings
|
// turn off superfluous verilog processor warnings
|
// altera message_level Level1
|
// altera message_level Level1
|
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
// altera message_off 10034 10035 10036 10037 10230 10240 10030
|
|
|
module ulight_fifo_fifo_empty_rx_status (
|
module ulight_fifo_fifo_empty_rx_status (
|
// inputs:
|
// inputs:
|
address,
|
address,
|
clk,
|
clk,
|
in_port,
|
in_port,
|
reset_n,
|
reset_n,
|
|
|
// outputs:
|
// outputs:
|
readdata
|
readdata
|
)
|
)
|
;
|
;
|
|
|
output [ 31: 0] readdata;
|
output [ 31: 0] readdata;
|
input [ 1: 0] address;
|
input [ 1: 0] address;
|
input clk;
|
input clk;
|
input in_port;
|
input in_port;
|
input reset_n;
|
input reset_n;
|
|
|
|
|
wire clk_en;
|
wire clk_en;
|
wire data_in;
|
wire data_in;
|
wire read_mux_out;
|
wire read_mux_out;
|
reg [ 31: 0] readdata;
|
reg [ 31: 0] readdata;
|
assign clk_en = 1;
|
assign clk_en = 1;
|
//s1, which is an e_avalon_slave
|
//s1, which is an e_avalon_slave
|
assign read_mux_out = {1 {(address == 0)}} & data_in;
|
assign read_mux_out = {1 {(address == 0)}} & data_in;
|
always @(posedge clk or negedge reset_n)
|
always @(posedge clk or negedge reset_n)
|
begin
|
begin
|
if (reset_n == 0)
|
if (reset_n == 0)
|
readdata <= 0;
|
readdata <= 0;
|
else if (clk_en)
|
else if (clk_en)
|
readdata <= {32'b0 | read_mux_out};
|
readdata <= {32'b0 | read_mux_out};
|
end
|
end
|
|
|
|
|
assign data_in = in_port;
|
assign data_in = in_port;
|
|
|
endmodule
|
endmodule
|
|
|
|
|
