// ulight_fifo_hps_0.v
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// ulight_fifo_hps_0.v
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// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
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// This file was auto-generated from altera_hps_hw.tcl. If you edit it your changes
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// will probably be lost.
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// will probably be lost.
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//
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//
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// Generated using ACDS version 17.0 598
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// Generated using ACDS version 17.1 593
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module ulight_fifo_hps_0 #(
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module ulight_fifo_hps_0 #(
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parameter F2S_Width = 0,
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parameter F2S_Width = 0,
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parameter S2F_Width = 1
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parameter S2F_Width = 1
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) (
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) (
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output wire h2f_rst_n, // h2f_reset.reset_n
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output wire h2f_rst_n, // h2f_reset.reset_n
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input wire h2f_axi_clk, // h2f_axi_clock.clk
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input wire h2f_axi_clk, // h2f_axi_clock.clk
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output wire [11:0] h2f_AWID, // h2f_axi_master.awid
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output wire [11:0] h2f_AWID, // h2f_axi_master.awid
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output wire [29:0] h2f_AWADDR, // .awaddr
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output wire [29:0] h2f_AWADDR, // .awaddr
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output wire [3:0] h2f_AWLEN, // .awlen
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output wire [3:0] h2f_AWLEN, // .awlen
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output wire [2:0] h2f_AWSIZE, // .awsize
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output wire [2:0] h2f_AWSIZE, // .awsize
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output wire [1:0] h2f_AWBURST, // .awburst
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output wire [1:0] h2f_AWBURST, // .awburst
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output wire [1:0] h2f_AWLOCK, // .awlock
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output wire [1:0] h2f_AWLOCK, // .awlock
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output wire [3:0] h2f_AWCACHE, // .awcache
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output wire [3:0] h2f_AWCACHE, // .awcache
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output wire [2:0] h2f_AWPROT, // .awprot
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output wire [2:0] h2f_AWPROT, // .awprot
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output wire h2f_AWVALID, // .awvalid
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output wire h2f_AWVALID, // .awvalid
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input wire h2f_AWREADY, // .awready
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input wire h2f_AWREADY, // .awready
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output wire [11:0] h2f_WID, // .wid
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output wire [11:0] h2f_WID, // .wid
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output wire [31:0] h2f_WDATA, // .wdata
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output wire [31:0] h2f_WDATA, // .wdata
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output wire [3:0] h2f_WSTRB, // .wstrb
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output wire [3:0] h2f_WSTRB, // .wstrb
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output wire h2f_WLAST, // .wlast
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output wire h2f_WLAST, // .wlast
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output wire h2f_WVALID, // .wvalid
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output wire h2f_WVALID, // .wvalid
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input wire h2f_WREADY, // .wready
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input wire h2f_WREADY, // .wready
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input wire [11:0] h2f_BID, // .bid
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input wire [11:0] h2f_BID, // .bid
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input wire [1:0] h2f_BRESP, // .bresp
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input wire [1:0] h2f_BRESP, // .bresp
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input wire h2f_BVALID, // .bvalid
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input wire h2f_BVALID, // .bvalid
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output wire h2f_BREADY, // .bready
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output wire h2f_BREADY, // .bready
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output wire [11:0] h2f_ARID, // .arid
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output wire [11:0] h2f_ARID, // .arid
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output wire [29:0] h2f_ARADDR, // .araddr
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output wire [29:0] h2f_ARADDR, // .araddr
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output wire [3:0] h2f_ARLEN, // .arlen
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output wire [3:0] h2f_ARLEN, // .arlen
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output wire [2:0] h2f_ARSIZE, // .arsize
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output wire [2:0] h2f_ARSIZE, // .arsize
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output wire [1:0] h2f_ARBURST, // .arburst
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output wire [1:0] h2f_ARBURST, // .arburst
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output wire [1:0] h2f_ARLOCK, // .arlock
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output wire [1:0] h2f_ARLOCK, // .arlock
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output wire [3:0] h2f_ARCACHE, // .arcache
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output wire [3:0] h2f_ARCACHE, // .arcache
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output wire [2:0] h2f_ARPROT, // .arprot
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output wire [2:0] h2f_ARPROT, // .arprot
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output wire h2f_ARVALID, // .arvalid
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output wire h2f_ARVALID, // .arvalid
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input wire h2f_ARREADY, // .arready
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input wire h2f_ARREADY, // .arready
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input wire [11:0] h2f_RID, // .rid
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input wire [11:0] h2f_RID, // .rid
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input wire [31:0] h2f_RDATA, // .rdata
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input wire [31:0] h2f_RDATA, // .rdata
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input wire [1:0] h2f_RRESP, // .rresp
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input wire [1:0] h2f_RRESP, // .rresp
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input wire h2f_RLAST, // .rlast
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input wire h2f_RLAST, // .rlast
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input wire h2f_RVALID, // .rvalid
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input wire h2f_RVALID, // .rvalid
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output wire h2f_RREADY, // .rready
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output wire h2f_RREADY, // .rready
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output wire [12:0] mem_a, // memory.mem_a
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output wire [12:0] mem_a, // memory.mem_a
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output wire [2:0] mem_ba, // .mem_ba
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output wire [2:0] mem_ba, // .mem_ba
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output wire mem_ck, // .mem_ck
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output wire mem_ck, // .mem_ck
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output wire mem_ck_n, // .mem_ck_n
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output wire mem_ck_n, // .mem_ck_n
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output wire mem_cke, // .mem_cke
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output wire mem_cke, // .mem_cke
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output wire mem_cs_n, // .mem_cs_n
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output wire mem_cs_n, // .mem_cs_n
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output wire mem_ras_n, // .mem_ras_n
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output wire mem_ras_n, // .mem_ras_n
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output wire mem_cas_n, // .mem_cas_n
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output wire mem_cas_n, // .mem_cas_n
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output wire mem_we_n, // .mem_we_n
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output wire mem_we_n, // .mem_we_n
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output wire mem_reset_n, // .mem_reset_n
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output wire mem_reset_n, // .mem_reset_n
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inout wire [7:0] mem_dq, // .mem_dq
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inout wire [7:0] mem_dq, // .mem_dq
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inout wire mem_dqs, // .mem_dqs
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inout wire mem_dqs, // .mem_dqs
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inout wire mem_dqs_n, // .mem_dqs_n
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inout wire mem_dqs_n, // .mem_dqs_n
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output wire mem_odt, // .mem_odt
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output wire mem_odt, // .mem_odt
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output wire mem_dm, // .mem_dm
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output wire mem_dm, // .mem_dm
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input wire oct_rzqin // .oct_rzqin
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input wire oct_rzqin // .oct_rzqin
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);
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);
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generate
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generate
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// If any of the display statements (or deliberately broken
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// If any of the display statements (or deliberately broken
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// instantiations) within this generate block triggers then this module
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// instantiations) within this generate block triggers then this module
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// has been instantiated this module with a set of parameters different
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// has been instantiated this module with a set of parameters different
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// from those it was generated for. This will usually result in a
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// from those it was generated for. This will usually result in a
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// non-functioning system.
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// non-functioning system.
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if (F2S_Width != 0)
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if (F2S_Width != 0)
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begin
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begin
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initial begin
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$display("Generated module instantiated with wrong parameters");
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$stop;
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$stop;
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end
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end
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instantiated_with_wrong_parameters_error_see_comment_above
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instantiated_with_wrong_parameters_error_see_comment_above
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f2s_width_check ( .error(1'b1) );
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f2s_width_check ( .error(1'b1) );
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end
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end
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if (S2F_Width != 1)
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if (S2F_Width != 1)
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begin
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begin
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initial begin
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initial begin
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$display("Generated module instantiated with wrong parameters");
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$display("Generated module instantiated with wrong parameters");
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$stop;
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$stop;
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end
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end
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instantiated_with_wrong_parameters_error_see_comment_above
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instantiated_with_wrong_parameters_error_see_comment_above
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s2f_width_check ( .error(1'b1) );
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s2f_width_check ( .error(1'b1) );
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end
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end
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endgenerate
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endgenerate
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ulight_fifo_hps_0_fpga_interfaces fpga_interfaces (
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ulight_fifo_hps_0_fpga_interfaces fpga_interfaces (
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.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
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.h2f_rst_n (h2f_rst_n), // h2f_reset.reset_n
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.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
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.h2f_axi_clk (h2f_axi_clk), // h2f_axi_clock.clk
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.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
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.h2f_AWID (h2f_AWID), // h2f_axi_master.awid
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.h2f_AWADDR (h2f_AWADDR), // .awaddr
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.h2f_AWADDR (h2f_AWADDR), // .awaddr
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.h2f_AWLEN (h2f_AWLEN), // .awlen
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.h2f_AWLEN (h2f_AWLEN), // .awlen
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.h2f_AWSIZE (h2f_AWSIZE), // .awsize
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.h2f_AWSIZE (h2f_AWSIZE), // .awsize
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.h2f_AWBURST (h2f_AWBURST), // .awburst
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.h2f_AWBURST (h2f_AWBURST), // .awburst
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.h2f_AWLOCK (h2f_AWLOCK), // .awlock
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.h2f_AWLOCK (h2f_AWLOCK), // .awlock
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.h2f_AWCACHE (h2f_AWCACHE), // .awcache
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.h2f_AWCACHE (h2f_AWCACHE), // .awcache
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.h2f_AWPROT (h2f_AWPROT), // .awprot
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.h2f_AWPROT (h2f_AWPROT), // .awprot
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.h2f_AWVALID (h2f_AWVALID), // .awvalid
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.h2f_AWVALID (h2f_AWVALID), // .awvalid
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.h2f_AWREADY (h2f_AWREADY), // .awready
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.h2f_AWREADY (h2f_AWREADY), // .awready
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.h2f_WID (h2f_WID), // .wid
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.h2f_WID (h2f_WID), // .wid
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.h2f_WDATA (h2f_WDATA), // .wdata
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.h2f_WDATA (h2f_WDATA), // .wdata
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.h2f_WSTRB (h2f_WSTRB), // .wstrb
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.h2f_WSTRB (h2f_WSTRB), // .wstrb
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.h2f_WLAST (h2f_WLAST), // .wlast
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.h2f_WLAST (h2f_WLAST), // .wlast
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.h2f_WVALID (h2f_WVALID), // .wvalid
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.h2f_WVALID (h2f_WVALID), // .wvalid
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.h2f_WREADY (h2f_WREADY), // .wready
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.h2f_WREADY (h2f_WREADY), // .wready
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.h2f_BID (h2f_BID), // .bid
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.h2f_BID (h2f_BID), // .bid
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.h2f_BRESP (h2f_BRESP), // .bresp
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.h2f_BRESP (h2f_BRESP), // .bresp
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.h2f_BVALID (h2f_BVALID), // .bvalid
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.h2f_BVALID (h2f_BVALID), // .bvalid
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.h2f_BREADY (h2f_BREADY), // .bready
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.h2f_BREADY (h2f_BREADY), // .bready
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.h2f_ARID (h2f_ARID), // .arid
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.h2f_ARID (h2f_ARID), // .arid
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.h2f_ARADDR (h2f_ARADDR), // .araddr
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.h2f_ARADDR (h2f_ARADDR), // .araddr
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.h2f_ARLEN (h2f_ARLEN), // .arlen
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.h2f_ARLEN (h2f_ARLEN), // .arlen
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.h2f_ARSIZE (h2f_ARSIZE), // .arsize
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.h2f_ARSIZE (h2f_ARSIZE), // .arsize
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.h2f_ARBURST (h2f_ARBURST), // .arburst
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.h2f_ARBURST (h2f_ARBURST), // .arburst
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.h2f_ARLOCK (h2f_ARLOCK), // .arlock
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.h2f_ARLOCK (h2f_ARLOCK), // .arlock
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.h2f_ARCACHE (h2f_ARCACHE), // .arcache
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.h2f_ARCACHE (h2f_ARCACHE), // .arcache
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.h2f_ARPROT (h2f_ARPROT), // .arprot
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.h2f_ARPROT (h2f_ARPROT), // .arprot
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.h2f_ARVALID (h2f_ARVALID), // .arvalid
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.h2f_ARVALID (h2f_ARVALID), // .arvalid
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.h2f_ARREADY (h2f_ARREADY), // .arready
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.h2f_ARREADY (h2f_ARREADY), // .arready
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.h2f_RID (h2f_RID), // .rid
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.h2f_RID (h2f_RID), // .rid
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.h2f_RDATA (h2f_RDATA), // .rdata
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.h2f_RDATA (h2f_RDATA), // .rdata
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.h2f_RRESP (h2f_RRESP), // .rresp
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.h2f_RRESP (h2f_RRESP), // .rresp
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.h2f_RLAST (h2f_RLAST), // .rlast
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.h2f_RLAST (h2f_RLAST), // .rlast
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.h2f_RVALID (h2f_RVALID), // .rvalid
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.h2f_RVALID (h2f_RVALID), // .rvalid
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.h2f_RREADY (h2f_RREADY) // .rready
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.h2f_RREADY (h2f_RREADY) // .rready
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);
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);
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ulight_fifo_hps_0_hps_io hps_io (
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ulight_fifo_hps_0_hps_io hps_io (
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.mem_a (mem_a), // memory.mem_a
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.mem_a (mem_a), // memory.mem_a
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.mem_ba (mem_ba), // .mem_ba
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.mem_ba (mem_ba), // .mem_ba
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.mem_ck (mem_ck), // .mem_ck
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.mem_ck (mem_ck), // .mem_ck
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.mem_ck_n (mem_ck_n), // .mem_ck_n
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.mem_ck_n (mem_ck_n), // .mem_ck_n
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.mem_cke (mem_cke), // .mem_cke
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.mem_cke (mem_cke), // .mem_cke
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.mem_cs_n (mem_cs_n), // .mem_cs_n
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.mem_cs_n (mem_cs_n), // .mem_cs_n
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.mem_ras_n (mem_ras_n), // .mem_ras_n
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.mem_ras_n (mem_ras_n), // .mem_ras_n
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.mem_cas_n (mem_cas_n), // .mem_cas_n
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.mem_cas_n (mem_cas_n), // .mem_cas_n
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.mem_we_n (mem_we_n), // .mem_we_n
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.mem_we_n (mem_we_n), // .mem_we_n
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.mem_reset_n (mem_reset_n), // .mem_reset_n
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.mem_reset_n (mem_reset_n), // .mem_reset_n
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.mem_dq (mem_dq), // .mem_dq
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.mem_dq (mem_dq), // .mem_dq
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.mem_dqs (mem_dqs), // .mem_dqs
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.mem_dqs (mem_dqs), // .mem_dqs
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.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
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.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
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.mem_odt (mem_odt), // .mem_odt
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.mem_odt (mem_odt), // .mem_odt
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.mem_dm (mem_dm), // .mem_dm
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.mem_dm (mem_dm), // .mem_dm
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.oct_rzqin (oct_rzqin) // .oct_rzqin
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.oct_rzqin (oct_rzqin) // .oct_rzqin
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);
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);
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endmodule
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endmodule
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