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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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// ulight_fifo_mm_interconnect_0.v
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// ulight_fifo_mm_interconnect_0.v
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// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
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// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
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// will probably be lost.
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// will probably be lost.
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//
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//
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// Generated using ACDS version 17.0 598
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// Generated using ACDS version 17.1 593
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`timescale 1 ps / 1 ps
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`timescale 1 ps / 1 ps
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module ulight_fifo_mm_interconnect_0 (
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module ulight_fifo_mm_interconnect_0 (
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input wire [11:0] hps_0_h2f_axi_master_awid, // hps_0_h2f_axi_master.awid
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input wire [11:0] hps_0_h2f_axi_master_awid, // hps_0_h2f_axi_master.awid
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input wire [29:0] hps_0_h2f_axi_master_awaddr, // .awaddr
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input wire [29:0] hps_0_h2f_axi_master_awaddr, // .awaddr
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