| Line 17... |
Line 17... |
input wire refclk1
|
input wire refclk1
|
);
|
);
|
|
|
altera_pll #(
|
altera_pll #(
|
.fractional_vco_multiplier("false"),
|
.fractional_vco_multiplier("false"),
|
.reference_clock_frequency("100.0 MHz"),
|
.reference_clock_frequency("50.0 MHz"),
|
.pll_fractional_cout(32),
|
.pll_fractional_cout(32),
|
.pll_dsm_out_sel("1st_order"),
|
.pll_dsm_out_sel("1st_order"),
|
.operation_mode("direct"),
|
.operation_mode("normal"),
|
.number_of_clocks(1),
|
.number_of_clocks(1),
|
.output_clock_frequency0("400.000000 MHz"),
|
.output_clock_frequency0("400.000000 MHz"),
|
.phase_shift0("0 ps"),
|
.phase_shift0("0 ps"),
|
.duty_cycle0(50),
|
.duty_cycle0(50),
|
.output_clock_frequency1("0 MHz"),
|
.output_clock_frequency1("0 MHz"),
|
| Line 78... |
Line 78... |
.output_clock_frequency17("0 MHz"),
|
.output_clock_frequency17("0 MHz"),
|
.phase_shift17("0 ps"),
|
.phase_shift17("0 ps"),
|
.duty_cycle17(50),
|
.duty_cycle17(50),
|
.pll_type("Cyclone V"),
|
.pll_type("Cyclone V"),
|
.pll_subtype("General"),
|
.pll_subtype("General"),
|
.m_cnt_hi_div(2),
|
.m_cnt_hi_div(4),
|
.m_cnt_lo_div(2),
|
.m_cnt_lo_div(4),
|
.n_cnt_hi_div(256),
|
.n_cnt_hi_div(256),
|
.n_cnt_lo_div(256),
|
.n_cnt_lo_div(256),
|
.m_cnt_bypass_en("false"),
|
.m_cnt_bypass_en("false"),
|
.n_cnt_bypass_en("true"),
|
.n_cnt_bypass_en("true"),
|
.m_cnt_odd_div_duty_en("false"),
|
.m_cnt_odd_div_duty_en("false"),
|
| Line 213... |
Line 213... |
.c_cnt_ph_mux_prst17(0),
|
.c_cnt_ph_mux_prst17(0),
|
.c_cnt_in_src17("ph_mux_clk"),
|
.c_cnt_in_src17("ph_mux_clk"),
|
.c_cnt_bypass_en17("true"),
|
.c_cnt_bypass_en17("true"),
|
.c_cnt_odd_div_duty_en17("false"),
|
.c_cnt_odd_div_duty_en17("false"),
|
.pll_vco_div(2),
|
.pll_vco_div(2),
|
.pll_cp_current(30),
|
.pll_cp_current(20),
|
.pll_bwctrl(2000),
|
.pll_bwctrl(4000),
|
.pll_output_clk_frequency("400.0 MHz"),
|
.pll_output_clk_frequency("400.0 MHz"),
|
.pll_fractional_division("1"),
|
.pll_fractional_division("1"),
|
.mimic_fbclk_type("none"),
|
.mimic_fbclk_type("gclk"),
|
.pll_fbclk_mux_1("glb"),
|
.pll_fbclk_mux_1("glb"),
|
.pll_fbclk_mux_2("m_cnt"),
|
.pll_fbclk_mux_2("fb_1"),
|
.pll_m_cnt_in_src("ph_mux_clk"),
|
.pll_m_cnt_in_src("ph_mux_clk"),
|
.pll_slf_rst("false"),
|
.pll_slf_rst("false"),
|
.refclk1_frequency("100.0 MHz"),
|
.refclk1_frequency("100.0 MHz"),
|
.pll_clk_loss_sw_en("true"),
|
.pll_clk_loss_sw_en("true"),
|
.pll_manu_clk_sw_en("false"),
|
.pll_manu_clk_sw_en("false"),
|
