| Line 63... |
Line 63... |
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 73
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Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
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Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
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Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
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Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
|
|
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
|
|
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
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Info: ulight_fifo.pll_0: Able to implement PLL with user settings
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Info: ulight_fifo.pll_0: Able to implement PLL with user settings
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Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
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Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
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Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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| Line 145... |
Line 147... |
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_empty_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fifo_empty_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_full_rx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.fifo_full_tx_status: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
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Info: ulight_fifo.fsm_info: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 73
|
Info: ulight_fifo.hps_0: HPS Main PLL counter settings: n = 0 m = 36
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Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
|
Info: ulight_fifo.hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
|
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
Warning: ulight_fifo.hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
|
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
Warning: ulight_fifo.hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
|
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
Warning: ulight_fifo.hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
|
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
Warning: ulight_fifo.hps_0: set_interface_assignment: Interface "hps_io" does not exist
|
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
|
Info: ulight_fifo.pll_0: The legal reference clock frequency is 5.0 MHz..800.0 MHz
|
|
Warning: ulight_fifo.pll_0: 'refclk1' is not the same frequency as 'refclk'. You must run Timequest at both frequencies to ensure timing closure
|
|
Warning: ulight_fifo.pll_0: The period difference between refclk and refclk1 is greater than 20%, automatic clock loss detection will not work
|
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
|
Info: ulight_fifo.pll_0: Able to implement PLL with user settings
|
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
|
Warning: ulight_fifo.pll_0.refclk1: Signal refclk1 has unknown type refclk1
|
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.timecode_ready_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.timecode_rx: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo.timecode_tx_ready: PIO inputs are not hardwired in test bench. Undefined values will be read from PIO inputs during simulation.
|
Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for QUARTUS_SYNTH
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Info: ulight_fifo: Generating ulight_fifo "ulight_fifo" for QUARTUS_SYNTH
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Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
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Warning: ulight_fifo: "No matching role found for clk_0:clk:clk_out (clk)"
|
Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
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Warning: ulight_fifo: "No matching role found for pll_0:refclk1:refclk1 (refclk1)"
|
Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
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Info: auto_start: Starting RTL generation for module 'ulight_fifo_auto_start'
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Info: auto_start: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7395_5796219648198440793.dir/0001_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0001_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]
|
Info: auto_start: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_auto_start --dir=/tmp/alt7485_7332943204255753946.dir/0002_auto_start_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0002_auto_start_gen//ulight_fifo_auto_start_component_configuration.pl --do_build_sim=0 ]
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Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
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Info: auto_start: Done RTL generation for module 'ulight_fifo_auto_start'
|
Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
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Info: auto_start: "ulight_fifo" instantiated altera_avalon_pio "auto_start"
|
Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
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Info: clock_sel: Starting RTL generation for module 'ulight_fifo_clock_sel'
|
Info: clock_sel: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7395_5796219648198440793.dir/0002_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0002_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]
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Info: clock_sel: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_clock_sel --dir=/tmp/alt7485_7332943204255753946.dir/0003_clock_sel_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0003_clock_sel_gen//ulight_fifo_clock_sel_component_configuration.pl --do_build_sim=0 ]
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Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
|
Info: clock_sel: Done RTL generation for module 'ulight_fifo_clock_sel'
|
Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
|
Info: clock_sel: "ulight_fifo" instantiated altera_avalon_pio "clock_sel"
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Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
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Info: counter_rx_fifo: Starting RTL generation for module 'ulight_fifo_counter_rx_fifo'
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Info: counter_rx_fifo: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7395_5796219648198440793.dir/0003_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0003_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]
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Info: counter_rx_fifo: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_counter_rx_fifo --dir=/tmp/alt7485_7332943204255753946.dir/0004_counter_rx_fifo_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0004_counter_rx_fifo_gen//ulight_fifo_counter_rx_fifo_component_configuration.pl --do_build_sim=0 ]
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Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
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Info: counter_rx_fifo: Done RTL generation for module 'ulight_fifo_counter_rx_fifo'
|
Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
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Info: counter_rx_fifo: "ulight_fifo" instantiated altera_avalon_pio "counter_rx_fifo"
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Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
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Info: data_flag_rx: Starting RTL generation for module 'ulight_fifo_data_flag_rx'
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Info: data_flag_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7395_5796219648198440793.dir/0004_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0004_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]
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Info: data_flag_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_flag_rx --dir=/tmp/alt7485_7332943204255753946.dir/0005_data_flag_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0005_data_flag_rx_gen//ulight_fifo_data_flag_rx_component_configuration.pl --do_build_sim=0 ]
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Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
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Info: data_flag_rx: Done RTL generation for module 'ulight_fifo_data_flag_rx'
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Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
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Info: data_flag_rx: "ulight_fifo" instantiated altera_avalon_pio "data_flag_rx"
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Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
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Info: data_info: Starting RTL generation for module 'ulight_fifo_data_info'
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Info: data_info: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7395_5796219648198440793.dir/0005_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0005_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]
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Info: data_info: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_data_info --dir=/tmp/alt7485_7332943204255753946.dir/0006_data_info_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0006_data_info_gen//ulight_fifo_data_info_component_configuration.pl --do_build_sim=0 ]
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Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
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Info: data_info: Done RTL generation for module 'ulight_fifo_data_info'
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Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
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Info: data_info: "ulight_fifo" instantiated altera_avalon_pio "data_info"
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Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
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Info: fifo_empty_rx_status: Starting RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
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Info: fifo_empty_rx_status: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7395_5796219648198440793.dir/0006_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0006_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]
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Info: fifo_empty_rx_status: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_fifo_empty_rx_status --dir=/tmp/alt7485_7332943204255753946.dir/0007_fifo_empty_rx_status_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0007_fifo_empty_rx_status_gen//ulight_fifo_fifo_empty_rx_status_component_configuration.pl --do_build_sim=0 ]
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Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
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Info: fifo_empty_rx_status: Done RTL generation for module 'ulight_fifo_fifo_empty_rx_status'
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Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
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Info: fifo_empty_rx_status: "ulight_fifo" instantiated altera_avalon_pio "fifo_empty_rx_status"
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Info: hps_0: "Running for module: hps_0"
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Info: hps_0: "Running for module: hps_0"
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Info: hps_0: HPS Main PLL counter settings: n = 0 m = 73
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Info: hps_0: HPS Main PLL counter settings: n = 0 m = 36
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Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 39
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Info: hps_0: HPS peripherial PLL counter settings: n = 0 m = 19
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Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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Warning: hps_0: "Configuration/HPS-to-FPGA user 0 clock frequency" (desired_cfg_clk_mhz) requested 100.0 MHz, but only achieved 97.368421 MHz
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Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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Warning: hps_0: 1 or more output clock frequencies cannot be achieved precisely, consider revising desired output clock frequencies.
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Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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Warning: hps_0: ODT is disabled. Enabling ODT (Mode Register 1) may improve signal integrity
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Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
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Warning: hps_0: set_interface_assignment: Interface "hps_io" does not exist
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Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
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Info: hps_0: "ulight_fifo" instantiated altera_hps "hps_0"
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Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
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Info: led_pio_test: Starting RTL generation for module 'ulight_fifo_led_pio_test'
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Info: led_pio_test: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7395_5796219648198440793.dir/0007_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0007_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]
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Info: led_pio_test: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_led_pio_test --dir=/tmp/alt7485_7332943204255753946.dir/0008_led_pio_test_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0008_led_pio_test_gen//ulight_fifo_led_pio_test_component_configuration.pl --do_build_sim=0 ]
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Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
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Info: led_pio_test: Done RTL generation for module 'ulight_fifo_led_pio_test'
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Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
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Info: led_pio_test: "ulight_fifo" instantiated altera_avalon_pio "led_pio_test"
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Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
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Info: pll_0: "ulight_fifo" instantiated altera_pll "pll_0"
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Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: Starting RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7395_5796219648198440793.dir/0009_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0009_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]
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Info: timecode_rx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_rx --dir=/tmp/alt7485_7332943204255753946.dir/0010_timecode_rx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0010_timecode_rx_gen//ulight_fifo_timecode_rx_component_configuration.pl --do_build_sim=0 ]
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Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: Done RTL generation for module 'ulight_fifo_timecode_rx'
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Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
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Info: timecode_rx: "ulight_fifo" instantiated altera_avalon_pio "timecode_rx"
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Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: Starting RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7395_5796219648198440793.dir/0010_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0010_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]
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Info: timecode_tx_data: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_timecode_tx_data --dir=/tmp/alt7485_7332943204255753946.dir/0011_timecode_tx_data_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0011_timecode_tx_data_gen//ulight_fifo_timecode_tx_data_component_configuration.pl --do_build_sim=0 ]
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Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: Done RTL generation for module 'ulight_fifo_timecode_tx_data'
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Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
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Info: timecode_tx_data: "ulight_fifo" instantiated altera_avalon_pio "timecode_tx_data"
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Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: Starting RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7395_5796219648198440793.dir/0011_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7395_5796219648198440793.dir/0011_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]
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Info: write_data_fifo_tx: Generation command is [exec /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/bin/perl -I /home/felipe/intelFPGA_lite/17.0/quartus/linux64/perl/lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/europa -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin/perl_lib -I /home/felipe/intelFPGA_lite/17.0/quartus/sopc_builder/bin -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/common -I /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio -- /home/felipe/intelFPGA_lite/17.0/quartus/../ip/altera/sopc_builder_ip/altera_avalon_pio/generate_rtl.pl --name=ulight_fifo_write_data_fifo_tx --dir=/tmp/alt7485_7332943204255753946.dir/0012_write_data_fifo_tx_gen/ --quartus_dir=/home/felipe/intelFPGA_lite/17.0/quartus --verilog --config=/tmp/alt7485_7332943204255753946.dir/0012_write_data_fifo_tx_gen//ulight_fifo_write_data_fifo_tx_component_configuration.pl --do_build_sim=0 ]
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Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: Done RTL generation for module 'ulight_fifo_write_data_fifo_tx'
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Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
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Info: write_data_fifo_tx: "ulight_fifo" instantiated altera_avalon_pio "write_data_fifo_tx"
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_001: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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Info: avalon_st_adapter_002: Inserting error_adapter: error_adapter_0
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