|
|
|
|
|
|
name="$${FILENAME}"
|
name="$${FILENAME}"
|
displayName="$${FILENAME}"
|
displayName="$${FILENAME}"
|
version="1.0"
|
version="1.0"
|
description=""
|
description=""
|
tags=""
|
tags=""
|
categories="System" />
|
categories="System" />
|
|
|
{
|
{
|
element auto_start
|
element auto_start
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "11";
|
value = "11";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element clk_0
|
element clk_0
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "0";
|
value = "0";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element clock_sel
|
element clock_sel
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "21";
|
value = "21";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element counter_rx_fifo
|
element counter_rx_fifo
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "24";
|
value = "24";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element counter_tx_fifo
|
element counter_tx_fifo
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "23";
|
value = "23";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element data_flag_rx
|
element data_flag_rx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "6";
|
value = "6";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element data_info
|
element data_info
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "20";
|
value = "20";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element data_read_en_rx
|
element data_read_en_rx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "7";
|
value = "7";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element fifo_empty_rx_status
|
element fifo_empty_rx_status
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "9";
|
value = "9";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element fifo_empty_tx_status
|
element fifo_empty_tx_status
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "16";
|
value = "16";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element fifo_full_rx_status
|
element fifo_full_rx_status
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "8";
|
value = "8";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element fifo_full_tx_status
|
element fifo_full_tx_status
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "15";
|
value = "15";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element fsm_info
|
element fsm_info
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "22";
|
value = "22";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element hps_0
|
element hps_0
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "1";
|
value = "1";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element led_pio_test
|
element led_pio_test
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "3";
|
value = "3";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element link_disable
|
element link_disable
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "12";
|
value = "12";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element link_start
|
element link_start
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "10";
|
value = "10";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element pll_0
|
element pll_0
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "2";
|
value = "2";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element timecode_ready_rx
|
element timecode_ready_rx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "5";
|
value = "5";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element timecode_rx
|
element timecode_rx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "4";
|
value = "4";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element timecode_tx_data
|
element timecode_tx_data
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "17";
|
value = "17";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element timecode_tx_enable
|
element timecode_tx_enable
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "18";
|
value = "18";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element timecode_tx_ready
|
element timecode_tx_ready
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "19";
|
value = "19";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element write_data_fifo_tx
|
element write_data_fifo_tx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "13";
|
value = "13";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
element write_en_tx
|
element write_en_tx
|
{
|
{
|
datum _sortIndex
|
datum _sortIndex
|
{
|
{
|
value = "14";
|
value = "14";
|
type = "int";
|
type = "int";
|
}
|
}
|
}
|
}
|
}
|
}
|
]]>
|
]]>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="auto_start_external_connection"
|
name="auto_start_external_connection"
|
internal="auto_start.external_connection"
|
internal="auto_start.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
|
|
name="clock_sel_external_connection"
|
name="clock_sel_external_connection"
|
internal="clock_sel.external_connection"
|
internal="clock_sel.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="counter_rx_fifo_external_connection"
|
name="counter_rx_fifo_external_connection"
|
internal="counter_rx_fifo.external_connection"
|
internal="counter_rx_fifo.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="counter_tx_fifo_external_connection"
|
name="counter_tx_fifo_external_connection"
|
internal="counter_tx_fifo.external_connection"
|
internal="counter_tx_fifo.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="data_flag_rx_external_connection"
|
name="data_flag_rx_external_connection"
|
internal="data_flag_rx.external_connection"
|
internal="data_flag_rx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="data_info_external_connection"
|
name="data_info_external_connection"
|
internal="data_info.external_connection"
|
internal="data_info.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="data_read_en_rx_external_connection"
|
name="data_read_en_rx_external_connection"
|
internal="data_read_en_rx.external_connection"
|
internal="data_read_en_rx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="fifo_empty_rx_status_external_connection"
|
name="fifo_empty_rx_status_external_connection"
|
internal="fifo_empty_rx_status.external_connection"
|
internal="fifo_empty_rx_status.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="fifo_empty_tx_status_external_connection"
|
name="fifo_empty_tx_status_external_connection"
|
internal="fifo_empty_tx_status.external_connection"
|
internal="fifo_empty_tx_status.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="fifo_full_rx_status_external_connection"
|
name="fifo_full_rx_status_external_connection"
|
internal="fifo_full_rx_status.external_connection"
|
internal="fifo_full_rx_status.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="fifo_full_tx_status_external_connection"
|
name="fifo_full_tx_status_external_connection"
|
internal="fifo_full_tx_status.external_connection"
|
internal="fifo_full_tx_status.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="fsm_info_external_connection"
|
name="fsm_info_external_connection"
|
internal="fsm_info.external_connection"
|
internal="fsm_info.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="led_pio_test_external_connection"
|
name="led_pio_test_external_connection"
|
internal="led_pio_test.external_connection"
|
internal="led_pio_test.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="link_disable_external_connection"
|
name="link_disable_external_connection"
|
internal="link_disable.external_connection"
|
internal="link_disable.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="link_start_external_connection"
|
name="link_start_external_connection"
|
internal="link_start.external_connection"
|
internal="link_start.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
|
|
|
|
name="pll_0_outclk0"
|
name="pll_0_outclk0"
|
internal="pll_0.outclk0"
|
internal="pll_0.outclk0"
|
type="clock"
|
type="clock"
|
dir="start" />
|
dir="start" />
|
|
|
|
|
name="timecode_ready_rx_external_connection"
|
name="timecode_ready_rx_external_connection"
|
internal="timecode_ready_rx.external_connection"
|
internal="timecode_ready_rx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="timecode_rx_external_connection"
|
name="timecode_rx_external_connection"
|
internal="timecode_rx.external_connection"
|
internal="timecode_rx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="timecode_tx_data_external_connection"
|
name="timecode_tx_data_external_connection"
|
internal="timecode_tx_data.external_connection"
|
internal="timecode_tx_data.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="timecode_tx_enable_external_connection"
|
name="timecode_tx_enable_external_connection"
|
internal="timecode_tx_enable.external_connection"
|
internal="timecode_tx_enable.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="timecode_tx_ready_external_connection"
|
name="timecode_tx_ready_external_connection"
|
internal="timecode_tx_ready.external_connection"
|
internal="timecode_tx_ready.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="write_data_fifo_tx_external_connection"
|
name="write_data_fifo_tx_external_connection"
|
internal="write_data_fifo_tx.external_connection"
|
internal="write_data_fifo_tx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
name="write_en_tx_external_connection"
|
name="write_en_tx_external_connection"
|
internal="write_en_tx.external_connection"
|
internal="write_en_tx.external_connection"
|
type="conduit"
|
type="conduit"
|
dir="end" />
|
dir="end" />
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="counter_rx_fifo"
|
name="counter_rx_fifo"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="counter_tx_fifo"
|
name="counter_tx_fifo"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="data_flag_rx"
|
name="data_flag_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="data_read_en_rx"
|
name="data_read_en_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="fifo_empty_rx_status"
|
name="fifo_empty_rx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="fifo_empty_tx_status"
|
name="fifo_empty_tx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="fifo_full_rx_status"
|
name="fifo_full_rx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="fifo_full_tx_status"
|
name="fifo_full_tx_status"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
|
Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional
|
|
|
|
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|
|
No,No,No,No,No,No,No,No
|
No,No,No,No,No,No,No,No
|
|
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|
name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
|
name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
|
value="100" />
|
value="100" />
|
|
|
|
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|
|
|
|
|
|
No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
|
No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
|
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|
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|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
|
No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No,No
|
|
|
0x000000000000000000
|
0x000000000000000000
|
|
|
|
|
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|
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|
|
|
|
|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}
|
{320000000 1600000000} {320000000 1000000000} {800000000 400000000 400000000}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
|
name="quartus_ini_hps_ip_enable_all_peripheral_fpga_interfaces"
|
value="false" />
|
value="false" />
|
|
|
|
|
name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
|
name="quartus_ini_hps_ip_enable_emac0_peripheral_fpga_interface"
|
value="false" />
|
value="false" />
|
|
|
name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
|
name="quartus_ini_hps_ip_enable_low_speed_serial_fpga_interfaces"
|
value="false" />
|
value="false" />
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="led_pio_test"
|
name="led_pio_test"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="link_disable"
|
name="link_disable"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Create an adjpllin signal to connect with an upstream PLL
|
Create an adjpllin signal to connect with an upstream PLL
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Automatic Switchover
|
Automatic Switchover
|
|
|
|
|
|
|
name="timecode_ready_rx"
|
name="timecode_ready_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="timecode_rx"
|
name="timecode_rx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="timecode_tx_data"
|
name="timecode_tx_data"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="timecode_tx_enable"
|
name="timecode_tx_enable"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="timecode_tx_ready"
|
name="timecode_tx_ready"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="write_data_fifo_tx"
|
name="write_data_fifo_tx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
name="write_en_tx"
|
name="write_en_tx"
|
kind="altera_avalon_pio"
|
kind="altera_avalon_pio"
|
version="17.0"
|
version="17.1"
|
enabled="1">
|
enabled="1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="led_pio_test.s1">
|
end="led_pio_test.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="timecode_rx.s1">
|
end="timecode_rx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="timecode_ready_rx.s1">
|
end="timecode_ready_rx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="data_flag_rx.s1">
|
end="data_flag_rx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="data_read_en_rx.s1">
|
end="data_read_en_rx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="fifo_full_rx_status.s1">
|
end="fifo_full_rx_status.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="fifo_empty_rx_status.s1">
|
end="fifo_empty_rx_status.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="link_start.s1">
|
end="link_start.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="auto_start.s1">
|
end="auto_start.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="link_disable.s1">
|
end="link_disable.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="write_data_fifo_tx.s1">
|
end="write_data_fifo_tx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="write_en_tx.s1">
|
end="write_en_tx.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="fifo_full_tx_status.s1">
|
end="fifo_full_tx_status.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="fifo_empty_tx_status.s1">
|
end="fifo_empty_tx_status.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="timecode_tx_data.s1">
|
end="timecode_tx_data.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="timecode_tx_enable.s1">
|
end="timecode_tx_enable.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="timecode_tx_ready.s1">
|
end="timecode_tx_ready.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="data_info.s1">
|
end="data_info.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="clock_sel.s1">
|
end="clock_sel.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="fsm_info.s1">
|
end="fsm_info.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="counter_tx_fifo.s1">
|
end="counter_tx_fifo.s1">
|
|
|
|
|
|
|
|
|
|
|
kind="avalon"
|
kind="avalon"
|
version="17.0"
|
version="17.1"
|
start="hps_0.h2f_axi_master"
|
start="hps_0.h2f_axi_master"
|
end="counter_rx_fifo.s1">
|
end="counter_rx_fifo.s1">
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_ready_rx.clk" />
|
end="timecode_ready_rx.clk" />
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="data_read_en_rx.clk" />
|
end="fifo_empty_rx_status.clk" />
|
|
|
|
|
|
|
|
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_full_rx_status.clk" />
|
end="timecode_tx_data.clk" />
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_empty_rx_status.clk" />
|
end="timecode_tx_ready.clk" />
|
|
|
|
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="write_data_fifo_tx.clk" />
|
end="counter_tx_fifo.clk" />
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_full_tx_status.clk" />
|
end="counter_rx_fifo.clk" />
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="fifo_empty_tx_status.clk" />
|
end="write_data_fifo_tx.clk" />
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_data.clk" />
|
end="timecode_tx_enable.clk" />
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_enable.clk" />
|
end="fifo_full_tx_status.clk" />
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="timecode_tx_ready.clk" />
|
end="fifo_full_rx_status.clk" />
|
|
|
|
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="counter_tx_fifo.clk" />
|
end="data_read_en_rx.clk" />
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="counter_rx_fifo.clk" />
|
end="fifo_empty_tx_status.clk" />
|
|
|
|
|
|
|
kind="clock"
|
kind="clock"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk"
|
start="clk_0.clk"
|
end="hps_0.h2f_axi_clock" />
|
end="hps_0.h2f_axi_clock" />
|
|
|
|
|
|
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="led_pio_test.reset" />
|
end="led_pio_test.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="timecode_rx.reset" />
|
end="timecode_rx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="timecode_ready_rx.reset" />
|
end="timecode_ready_rx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="data_flag_rx.reset" />
|
end="data_flag_rx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="data_read_en_rx.reset" />
|
end="data_read_en_rx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="fifo_full_rx_status.reset" />
|
end="fifo_full_rx_status.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="fifo_empty_rx_status.reset" />
|
end="fifo_empty_rx_status.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="link_start.reset" />
|
end="link_start.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="auto_start.reset" />
|
end="auto_start.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="link_disable.reset" />
|
end="link_disable.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="write_data_fifo_tx.reset" />
|
end="write_data_fifo_tx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="write_en_tx.reset" />
|
end="write_en_tx.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="fifo_full_tx_status.reset" />
|
end="fifo_full_tx_status.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="fifo_empty_tx_status.reset" />
|
end="fifo_empty_tx_status.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="timecode_tx_data.reset" />
|
end="timecode_tx_data.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="timecode_tx_enable.reset" />
|
end="timecode_tx_enable.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="timecode_tx_ready.reset" />
|
end="timecode_tx_ready.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="data_info.reset" />
|
end="data_info.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="clock_sel.reset" />
|
end="clock_sel.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="fsm_info.reset" />
|
end="fsm_info.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="counter_tx_fifo.reset" />
|
end="counter_tx_fifo.reset" />
|
|
|
kind="reset"
|
kind="reset"
|
version="17.0"
|
version="17.1"
|
start="clk_0.clk_reset"
|
start="clk_0.clk_reset"
|
end="counter_rx_fifo.reset" />
|
end="counter_rx_fifo.reset" />
|
|
|
|
|
|
|
|
|
|
|
|
|
