| Line 33... |
Line 33... |
module detector_tokens(
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module detector_tokens(
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input rx_din,
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input rx_din,
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input rx_sin,
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input rx_sin,
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input rx_resetn,
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input rx_resetn,
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//input clock_sys,
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//input clock_sys,
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output reg rx_buffer_write,
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//output reg rx_buffer_write,
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output reg [13:0] info
|
output reg [13:0] info
|
);
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);
|
|
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reg rx_error;
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wire rx_error;
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wire rx_got_bit;
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reg rx_got_bit;
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reg rx_got_null;
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reg rx_got_null;
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reg rx_got_nchar;
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reg rx_got_nchar;
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reg rx_got_time_code;
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reg rx_got_time_code;
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reg rx_got_fct;
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reg rx_got_fct;
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|
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reg [4:0] counter_neg;
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wire [5:0] counter_neg;
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//reg [3:0] counter_control;
|
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//reg [3:0] counter_data;
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reg [1:0] state_data_process;
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//reg [5:0] counter_bit_found;
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reg [1:0] next_state_data_process;
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reg control_bit_found;
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reg control_bit_found;
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|
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wire posedge_clk;
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wire posedge_clk;
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wire negedge_clk;
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wire negedge_clk;
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|
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reg bit_c_0;//N
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wire bit_c_0;//N
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reg bit_c_1;//P
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wire bit_c_1;//P
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reg bit_c_2;//N
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wire bit_c_2;//N
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reg bit_c_3;//P
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wire bit_c_3;//P
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reg bit_c_ex;//P
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wire bit_c_ex;//P
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|
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reg bit_d_0;//N
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wire bit_d_0;//N
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reg bit_d_1;//P
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wire bit_d_1;//P
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reg bit_d_2;//N
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wire bit_d_2;//N
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reg bit_d_3;//P
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wire bit_d_3;//P
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reg bit_d_4;//N
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wire bit_d_4;//N
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reg bit_d_5;//P
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wire bit_d_5;//P
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reg bit_d_6;//N
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wire bit_d_6;//N
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reg bit_d_7;//P
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wire bit_d_7;//P
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reg bit_d_8;//N
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wire bit_d_8;//N
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reg bit_d_9;//P
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wire bit_d_9;//P
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//reg bit_d_ex;//P
|
|
|
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reg is_control;
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wire is_control;
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reg is_data;
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reg is_data;
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|
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reg last_is_control;
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reg last_is_control;
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reg last_is_data;
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reg last_is_data;
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reg last_is_timec;
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//reg last_is_timec;
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|
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reg last_was_control;
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reg last_was_control;
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reg last_was_data;
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reg last_was_data;
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reg last_was_timec;
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reg last_was_timec;
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|
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reg [3:0] control;
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reg [3:0] control;
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reg [3:0] control_r;
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reg [3:0] control_r;
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reg [3:0] control_p_r;
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reg [9:0] data;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [9:0] timecode;
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|
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reg [9:0] dta_timec;
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reg [9:0] dta_timec;
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reg [9:0] dta_timec_p;
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|
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reg [3:0] control_l_r;
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reg [3:0] control_l_r;
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reg [9:0] data_l_r;
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reg [9:0] data_l_r;
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|
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//reg parity_error;
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reg parity_rec_c;
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//wire check_c_d;
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reg parity_rec_d;
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|
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reg rx_data_take;
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reg rx_data_take_0;
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|
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//wire [13:0] info_w;
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reg rx_error_c;
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reg first_time;
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reg rx_error_d;
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|
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wire ready_control;
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reg ready_control;
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wire ready_data;
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reg ready_data;
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|
|
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reg parity_rec_c_gen;
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reg parity_rec_d_gen;
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|
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//CLOCK RECOVERY
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reg ready_control_p;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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reg ready_data_p;
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assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;
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|
|
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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reg ready_control_p_r;
|
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reg ready_data_p_r;
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|
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assign ready_control = is_control;
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wire posedge_p;
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assign ready_data = (counter_neg == 5'd5)?is_data:1'b0;
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|
|
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always@(posedge posedge_clk or negedge rx_resetn)
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reg f_time;
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begin
|
|
|
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if(!rx_resetn)
|
//CLOCK RECOVERY
|
begin
|
assign posedge_clk = posedge_p;
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bit_d_1 <= 1'b0;
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assign negedge_clk = (f_time)?!posedge_p:1'b0;
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bit_d_3 <= 1'b0;
|
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
|
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bit_d_9 <= 1'b0;
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first_time <= 1'b0;
|
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end
|
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else
|
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begin
|
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bit_d_1 <= rx_din;
|
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bit_d_3 <= bit_d_1;
|
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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first_time <= 1'b1;
|
|
|
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end
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assign rx_error = rx_error_c | rx_error_d;
|
|
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end
|
buf (posedge_p,rx_din ^ rx_sin);
|
|
|
always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
bit_c_1 <= 1'b0;
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f_time <= 1'b0;
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bit_c_3 <= 1'b0;
|
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bit_c_ex <= 1'b0;
|
|
end
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end
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else
|
else
|
begin
|
begin
|
bit_c_1 <= rx_din;
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f_time <= 1'b1;
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bit_c_3 <= bit_c_1;
|
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bit_c_ex <= bit_c_3;
|
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end
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end
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|
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end
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end
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|
|
|
always@(*)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
rx_got_bit = 1'b0;
|
begin
|
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bit_d_0 <= 1'b0;
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if(rx_din | rx_sin)
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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end
|
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else
|
|
begin
|
begin
|
bit_d_0 <= rx_din;
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rx_got_bit = 1'b1;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
|
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
|
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end
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end
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end
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end
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|
|
|
always@(*)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
|
begin
|
begin
|
|
|
if(!rx_resetn)
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ready_control = 1'b0;
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ready_data = 1'b0;
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|
|
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if(is_control && counter_neg[5:0] == 6'd4 && !posedge_p)
|
begin
|
begin
|
bit_c_0 <= 1'b0;
|
ready_control = 1'b1;
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bit_c_2 <= 1'b0;
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ready_data = 1'b0;
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end
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end
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else
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else if(is_control && counter_neg[5:0] == 6'd32 && !posedge_p)
|
begin
|
begin
|
|
ready_control = 1'b0;
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bit_c_0 <= rx_din;
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ready_data = 1'b1;
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bit_c_2 <= bit_c_0;
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|
end
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end
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end
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end
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|
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always@(posedge negedge_clk or negedge rx_resetn)
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bit_capture_data capture_d(
|
begin
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.negedge_clk(negedge_clk),
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.posedge_clk(posedge_clk),
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.rx_resetn(rx_resetn),
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|
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if(!rx_resetn)
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.rx_din(rx_din),
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begin
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is_control <= 1'b0;
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is_data <= 1'b0;
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control_bit_found <= 1'b0;
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counter_neg <= 5'd0;
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end
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else
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begin
|
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if(counter_neg == 5'd0)
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begin
|
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control_bit_found <= rx_din;
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is_control <= 1'b0;
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is_data <= 1'b0;
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counter_neg <= counter_neg + 5'd1;
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end
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else if(counter_neg == 5'd1 && control_bit_found)
|
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begin
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is_control <= 1'b1;
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is_data <= 1'b0;
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counter_neg <= counter_neg + 5'd1;
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end
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else if(counter_neg == 5'd1 && !control_bit_found)
|
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begin
|
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is_control <= 1'b0;
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is_data <= 1'b1;
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counter_neg <= counter_neg + 5'd1;
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end
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else
|
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begin
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|
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if(is_control)
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.bit_d_0(bit_d_0),//N
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begin
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.bit_d_1(bit_d_1),//P
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control_bit_found <= rx_din;
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.bit_d_2(bit_d_2),//N
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.bit_d_3(bit_d_3),//P
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.bit_d_4(bit_d_4),//N
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.bit_d_5(bit_d_5),//P
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.bit_d_6(bit_d_6),//N
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.bit_d_7(bit_d_7),//P
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.bit_d_8(bit_d_8),//N
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.bit_d_9(bit_d_9)//P
|
|
);
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|
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if(counter_neg == 5'd2)
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bit_capture_control capture_c(
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begin
|
.negedge_clk(negedge_clk),
|
counter_neg <= 5'd1;
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.posedge_clk(posedge_clk),
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is_control <= 1'b0;
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.rx_resetn(rx_resetn),
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is_data <= 1'b0;
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end
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.rx_din(rx_din),
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end
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else if(is_data)
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.bit_c_0(bit_c_0),
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begin
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.bit_c_1(bit_c_1),
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if(counter_neg == 5'd5)
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.bit_c_2(bit_c_2),
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begin
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.bit_c_3(bit_c_3)
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control_bit_found <= rx_din;
|
);
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counter_neg <= 5'd1;
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is_data <= 1'b0;
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is_control <= 1'b0;
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end
|
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else
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counter_neg <= counter_neg + 5'd1;
|
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end
|
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end
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|
|
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end
|
counter_neg cnt_neg(
|
end
|
.negedge_clk(negedge_clk),
|
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.rx_resetn(rx_resetn),
|
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.rx_din(rx_din),
|
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.is_control(is_control),
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.counter_neg(counter_neg)
|
|
);
|
|
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always@(posedge negedge_clk or negedge rx_resetn)
|
always@(*)
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
next_state_data_process = state_data_process;
|
begin
|
|
rx_error <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
if(last_is_control)
|
|
begin
|
|
if(last_was_control)
|
|
begin
|
|
if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
|
|
begin
|
|
rx_error <= 1'b1;
|
|
end
|
|
end
|
|
else if(last_was_timec)
|
|
begin
|
|
if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
|
|
begin
|
|
rx_error <= 1'b1;
|
|
end
|
|
end
|
|
else if(last_was_data)
|
|
begin
|
|
if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
|
|
begin
|
|
rx_error <= 1'b1;
|
|
end
|
|
end
|
|
|
|
end
|
case(state_data_process)
|
else if(last_is_data)
|
2'd0:
|
begin
|
|
if(last_was_control)
|
|
begin
|
begin
|
if(!(data[8]^control[1]^control[0]) != data[9])
|
if(ready_control_p_r || ready_data_p_r)
|
begin
|
begin
|
rx_error <= 1'b1;
|
next_state_data_process = 2'd1;
|
end
|
end
|
end
|
else
|
else if(last_was_timec)
|
|
begin
|
|
if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
|
|
begin
|
begin
|
rx_error <= 1'b1;
|
next_state_data_process = 2'd0;
|
end
|
end
|
end
|
end
|
else if(last_was_data)
|
2'd1:
|
begin
|
begin
|
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
|
next_state_data_process = 2'd0;
|
begin
|
|
rx_error <= 1'b1;
|
|
end
|
|
end
|
|
end
|
end
|
|
default:
|
|
begin
|
|
next_state_data_process = 2'd0;
|
end
|
end
|
|
endcase
|
end
|
end
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
| Line 374... |
Line 287... |
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
rx_buffer_write <= 1'b0;
|
ready_control_p_r <= 1'b0;
|
rx_data_take_0 <= 1'b0;
|
ready_data_p_r <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_data_take_0 <= rx_data_take;
|
|
rx_buffer_write <= rx_data_take_0;
|
if(counter_neg[5:0] == 6'd4 && is_control)
|
|
begin
|
|
ready_control_p_r <= 1'b1;
|
|
end
|
|
else if(counter_neg[5:0] == 6'd32)
|
|
begin
|
|
ready_data_p_r <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
ready_control_p_r <= 1'b0;
|
|
ready_data_p_r <= 1'b0;
|
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge ready_control or negedge rx_resetn )
|
always@(posedge posedge_clk or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control_r <= 4'd0;
|
control_r <= 4'd0;
|
|
parity_rec_c <= 1'b0;
|
|
parity_rec_c_gen <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(counter_neg == 5'd2)
|
|
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
else if(counter_neg == 5'd1 && control == 4'd7)
|
parity_rec_c <= bit_c_3;
|
control_r <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};
|
|
else
|
if(last_is_control)
|
control_r <= control_r;
|
begin
|
|
parity_rec_c_gen <= !(bit_c_2^control[0]^control[1]);
|
|
end
|
|
else if(last_is_data)
|
|
begin
|
|
parity_rec_c_gen <= !(bit_c_2^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
|
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge ready_data or negedge rx_resetn )
|
always@(posedge posedge_clk or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
dta_timec <= 10'd0;
|
dta_timec <= 10'd0;
|
|
parity_rec_d <= 1'b0;
|
|
parity_rec_d_gen <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(counter_neg == 5'd5)
|
|
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
else
|
parity_rec_d <= bit_d_9;
|
dta_timec <= dta_timec;
|
|
|
if(last_is_control)
|
|
begin
|
|
parity_rec_d_gen <= !(bit_d_8^control[0]^control[1]);
|
|
end
|
|
else if(last_is_data)
|
|
begin
|
|
parity_rec_d_gen <= !(bit_d_8^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]);
|
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge posedge_clk or negedge rx_resetn )
|
always@(posedge posedge_clk or negedge rx_resetn )
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control <= 4'd0;
|
|
control_l_r <= 4'd0;
|
control_l_r <= 4'd0;
|
|
control <= 4'd0;
|
data <= 10'd0;
|
data <= 10'd0;
|
data_l_r <= 10'd0;
|
|
//rx_data_flag <= 9'd0;
|
|
//rx_buffer_write <= 1'b0;
|
|
//rx_data_take <= 1'b0;
|
|
|
|
timecode <= 10'd0;
|
|
// rx_time_out <= 8'd0;
|
|
// rx_tick_out <= 1'b0;
|
|
|
|
last_is_control <=1'b0;
|
last_is_control <=1'b0;
|
last_is_data <=1'b0;
|
last_is_data <=1'b0;
|
last_is_timec <=1'b0;
|
//last_is_timec <= 1'b0;
|
|
|
last_was_control <=1'b0;
|
|
last_was_data <=1'b0;
|
|
last_was_timec <=1'b0;
|
|
|
|
|
state_data_process <= 2'd0;
|
info <= 14'd0;
|
info <= 14'd0;
|
//rx_error <= 1'b0;
|
|
//rx_got_null <= 1'b0;
|
|
//rx_got_nchar <= 1'b0;
|
|
//rx_got_time_code <= 1'b0;
|
|
//rx_got_fct <= 1'b0;
|
|
|
|
//meta_hold_setup <= 1'b0;
|
|
//meta_hold_setup_n <= 1'b0;
|
|
//meta_hold_setup_n_n<= 1'b0;
|
|
|
|
|
rx_error_c <= 1'b0;
|
|
rx_error_d <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
//meta_hold_setup_n_n <= meta_hold_setup;
|
state_data_process <= next_state_data_process;
|
//meta_hold_setup_n <= meta_hold_setup_n_n;
|
|
|
|
if(ready_control)
|
case(state_data_process)
|
|
2'd0:
|
begin
|
begin
|
control <= control_r;
|
|
|
if(ready_control_p_r)
|
|
begin
|
|
control <= control_p_r;
|
control_l_r <= control;
|
control_l_r <= control;
|
|
|
last_is_control <= 1'b1;
|
last_is_control <= 1'b1;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b0;
|
//last_is_timec <= 1'b0;
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
|
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
|
|
|
end
|
end
|
else if(ready_data)
|
else if(ready_data_p_r)
|
begin
|
begin
|
if(control[2:0] != 3'd7)
|
if(control[2:0] != 3'd7)
|
begin
|
begin
|
data <= dta_timec;
|
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
|
|
last_is_control <=1'b0;
|
last_is_control <=1'b0;
|
last_is_data <=1'b1;
|
last_is_data <=1'b1;
|
last_is_timec <=1'b0;
|
//last_is_timec <=1'b0;
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
|
end
|
end
|
else if(control[2:0] == 3'd7)
|
else if(control[2:0] == 3'd7)
|
begin
|
begin
|
timecode <= dta_timec;
|
|
last_is_control <= 1'b0;
|
last_is_control <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b1;
|
//last_is_timec <= 1'b1;
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
|
end
|
end
|
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
|
end
|
end
|
else if(last_is_data)
|
else
|
begin
|
begin
|
|
|
data_l_r <= data;
|
end
|
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
|
|
|
rx_data_take <= 1'b1;
|
|
//rx_tick_out <= 1'b0;
|
|
|
|
//meta_hold_setup <= 1'b0;
|
|
end
|
end
|
else if(last_is_timec)
|
2'd1:
|
|
begin
|
|
if(ready_control_p_r)
|
begin
|
begin
|
//rx_tick_out <= 1'b1;
|
|
rx_data_take <= 1'b1;
|
|
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
if(parity_rec_c_gen != parity_rec_c)
|
|
begin
|
|
rx_error_c <= 1'b1;
|
|
end
|
|
else
|
|
rx_error_c <= rx_error_c;
|
|
|
//meta_hold_setup <= 1'b0;
|
|
end
|
end
|
else if(last_is_control)
|
else if(ready_data_p_r)
|
begin
|
begin
|
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
if(parity_rec_d_gen != parity_rec_d)
|
|
|
rx_data_take <= 1'b0;
|
|
|
|
if((control[2:0] == 3'd6) == 1'b1 )
|
|
begin
|
|
data <= 10'b0100000001;
|
|
end
|
|
else if( (control[2:0] == 3'd5 ) == 1'b1 )
|
|
begin
|
begin
|
data <= 10'b0100000000;
|
rx_error_d <= 1'b1;
|
end
|
end
|
|
else
|
|
rx_error_d <= rx_error_d;
|
|
|
|
|
end
|
end
|
else
|
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
info <= {control_l_r,control,rx_error,rx_got_bit,rx_got_null,rx_got_nchar,rx_got_time_code,rx_got_fct};
|
|
end
|
|
default:
|
|
begin
|
|
|
end
|
end
|
|
endcase
|
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
