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https://opencores.org/ocsvn/spacewiresystemc/spacewiresystemc/trunk
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Rev 40 |
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Line 30... |
//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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module write_axi(
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module write_axi(
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input clock_recovery,
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input clock_recovery,
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input clock_50,
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input reset_n,
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input reset_n,
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input [13:0] data_rec,
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input [13:0] data_rec,
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output reg [13:0] data_stand
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output reg [13:0] data_stand
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);
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);
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always@(posedge clock_recovery or negedge reset_n )
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always@(posedge clock_50 or negedge reset_n )
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begin
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begin
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if(!reset_n)
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if(!reset_n)
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begin
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begin
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data_stand <= 14'd0;
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data_stand <= 14'd0;
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end
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end
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else
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else
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begin
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begin
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if(clock_recovery)
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data_stand <= data_rec;
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data_stand <= data_rec;
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else
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data_stand <= data_stand;
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end
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end
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end
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end
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endmodule
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endmodule
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