//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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|
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module RX_SPW (
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module RX_SPW (
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input rx_din,
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input rx_din,
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input rx_sin,
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input rx_sin,
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|
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input rx_resetn,
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input rx_resetn,
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output rx_error,
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output rx_error,
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output rx_got_bit,
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output rx_got_bit,
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output rx_got_null,
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output rx_got_null,
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output rx_got_nchar,
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output rx_got_nchar,
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output rx_got_time_code,
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output rx_got_time_code,
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output rx_got_fct,
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output rx_got_fct,
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|
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output [8:0] rx_data_flag,
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output [8:0] rx_data_flag,
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output rx_buffer_write,
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output rx_buffer_write,
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|
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output [7:0] rx_time_out,
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output [7:0] rx_time_out,
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output rx_tick_out
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output rx_tick_out
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);
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);
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|
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wire [4:0] counter;
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reg [4:0] counter_pos;
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reg [4:0] counter_neg;
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reg [4:0] counter_neg;
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|
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wire posedge_clk;
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wire posedge_clk;
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wire negedge_clk;
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wire negedge_clk;
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|
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wire [3:0] control;
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reg bit_c_0;//N
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wire [9:0] data;
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reg bit_c_1;//P
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wire [9:0] timecode;
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reg bit_c_2;//N
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reg bit_c_3;//P
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reg [3:0] control_l_a;
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reg [9:0] data_l_a;
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reg bit_d_0;//N
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reg [9:0] timecode_l_a;
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reg bit_d_1;//P
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reg bit_d_2;//N
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reg [2:0] control_l_r;
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reg bit_d_3;//P
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reg [9:0] data_l_r;
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reg bit_d_4;//N
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reg [9:0] timecode_l_r;
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reg bit_d_5;//P
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reg bit_d_6;//N
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reg parity_error;
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reg bit_d_7;//P
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reg bit_d_8;//N
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reg control_found;
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reg bit_d_9;//P
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reg data_found;
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reg time_code_found;
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reg is_control;
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reg is_data;
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reg last_is_control;
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reg last_is_data;
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reg last_is_timec;
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reg last_was_control;
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reg last_was_control;
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reg last_was_data;
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reg last_was_data;
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reg last_was_time_code;
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reg last_was_timec;
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wire data_control_up;
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reg [3:0] control;
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reg [9:0] data;
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reg [9:0] timecode;
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assign data_control_up = (counter == 5'd3 & control[2:2])?1'b1:
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reg [3:0] control_l_r;
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(counter == 5'd9 & !control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:
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reg [9:0] data_l_r;
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(counter == 5'd9 & control_l_a[2:0] == 3'd7)?1'b1:1'b0;
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reg parity_error;
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wire check_c_d;
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//CLOCK RECOVERY
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign negedge_clk = (!(rx_din ^ rx_sin))?1'b1:1'b0;
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assign counter = counter_pos + counter_neg;
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assign check_c_d = ((is_control & counter_neg == 5'd2) == 1'b1 | (control[2:0] != 3'd7 & is_data & counter_neg == 5'd5) == 1'b1 | (control[2:0] == 3'd7 & is_data & counter_neg == 5'd5) == 1'b1)? 1'b1: 1'b0;
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assign rx_got_null = (control_l_r[2:0] == 3'd7 & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_fct = (control_l_r[2:0] != 3'd7 & control[2:0] == 3'd4 & check_c_d)?1'b1:1'b0;
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assign data[9:9] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:data[9:9];
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assign data[8:8] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:data[8:8];
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assign data[0:0] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:data[0:0];
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assign data[1:1] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:data[1:1];
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assign data[2:2] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:data[2:2];
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assign data[3:3] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:data[3:3];
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assign data[4:4] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:data[4:4];
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assign data[5:5] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:data[5:5];
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assign data[6:6] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:data[6:6];
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assign data[7:7] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:data[7:7];
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assign timecode[0:0] = (!rx_resetn)?1'b0:(counter == 5'd0)?rx_din:timecode[0:0];
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assign timecode[1:1] = (!rx_resetn)?1'b0:(counter == 5'd1)?rx_din:timecode[1:1];
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assign timecode[2:2] = (!rx_resetn)?1'b0:(counter == 5'd2)?rx_din:timecode[2:2];
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assign timecode[3:3] = (!rx_resetn)?1'b0:(counter == 5'd3)?rx_din:timecode[3:3];
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assign timecode[4:4] = (!rx_resetn)?1'b0:(counter == 5'd4)?rx_din:timecode[4:4];
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assign timecode[5:5] = (!rx_resetn)?1'b0:(counter == 5'd5)?rx_din:timecode[5:5];
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assign timecode[6:6] = (!rx_resetn)?1'b0:(counter == 5'd6)?rx_din:timecode[6:6];
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assign timecode[7:7] = (!rx_resetn)?1'b0:(counter == 5'd7)?rx_din:timecode[7:7];
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assign timecode[8:8] = (!rx_resetn)?1'b0:(counter == 5'd8)?rx_din:timecode[8:8];
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assign timecode[9:9] = (!rx_resetn)?1'b0:(counter == 5'd9)?rx_din:timecode[9:9];
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assign control[0:0] = (counter == 5'd3)?rx_din:control[0:0];
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assign control[1:1] = (counter == 5'd2)?rx_din:control[1:1];
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assign control[2:2] = (counter == 5'd1)?rx_din:control[2:2];
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assign control[3:3] = (counter == 5'd0)?rx_din:control[3:3];
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assign rx_got_fct = (counter == 5'd3 & control_l_a[2:0] != 3'd7 & control[2:2] & control[2:0] == 3'd4)?1'b1:1'b0;
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assign rx_got_nchar = (!control_l_a[2:2] & data_l_a[2:0] != 3'd7)?1'b1:1'b0;
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assign rx_got_time_code = (counter == 5'd9 & control_l_a[2:0] == 3'd7)? 1'b1:1'b0;
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assign rx_got_null = (counter == 5'd3 & control_l_r[2:0] == 3'd7 & control_l_a[2:0] == 3'd4)? 1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_got_bit = (posedge_clk)?1'b1:1'b0;
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assign rx_error = (parity_error)?1'b1:
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assign rx_error = parity_error;
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((counter == 5'd9 | counter == 5'd4) & !rx_got_fct & !rx_got_nchar & !rx_got_time_code & !rx_got_null & !last_was_control)?1'b1:1'b0;
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assign rx_data_flag = (rx_got_nchar)?data[8:0]:data_l_a[8:0];
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assign rx_got_nchar = (control[2:0] != 3'd7 & is_data)?1'b1:1'b0;
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assign rx_buffer_write = (rx_got_nchar & data_control_up)?1'b1:1'b0;
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assign rx_got_time_code = (control[2:0] == 3'd7 & is_data)?1'b1:1'b0;
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assign rx_time_out = (rx_got_time_code)?timecode[7:0]:timecode_l_a[7:0];
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assign rx_buffer_write = ( (control[2:0] == 3'd5 & is_control) == 1'b1 | (control[2:0] != 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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assign rx_tick_out = (rx_got_time_code & data_control_up)?1'b1:1'b0;
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assign rx_data_flag = ( (control[2:0] == 3'd6 & is_control) == 1'b1 )?9'b100000001:
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( (control[2:0] == 3'd5 & is_control) == 1'b1 )?9'b100000000:
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( (control[2:0] != 3'd7 & is_data) == 1'b1)?data[8:0]:9'd0;
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assign rx_time_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?timecode[7:0]:8'd0;
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assign rx_tick_out = ((control[2:0] == 3'd7 & is_data) == 1'b1)?1'b1:1'b0;
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always@(posedge posedge_clk or negedge rx_resetn or posedge last_was_control)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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begin
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if(!rx_resetn | last_was_control)
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if(!rx_resetn)
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begin
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begin
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counter_pos <= 5'd0;
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bit_c_1 <= 1'b0;
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bit_c_3 <= 1'b0;
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bit_d_1 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_9 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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if(counter == 5'd4 & control[2:2])
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bit_c_1 <= rx_din;
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begin
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bit_c_3 <= bit_c_1;
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counter_pos <= 5'd0;
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bit_d_1 <= rx_din;
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bit_d_3 <= bit_d_1;
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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end
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end
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end
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else if(counter == 5'd9)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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if(!rx_resetn)
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begin
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begin
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counter_pos <= 5'd0;
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bit_c_0 <= 1'b0;
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bit_c_2 <= 1'b0;
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bit_d_0 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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is_control <= 1'b0;
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is_data <= 1'b0;
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counter_neg <= 5'd0;
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end
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end
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else
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else
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begin
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begin
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counter_pos <= counter_pos + 5'd1;
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end
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bit_c_0 <= rx_din;
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bit_c_2 <= bit_c_0;
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bit_d_0 <= rx_din;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
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if(counter_neg == 5'd1)
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begin
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if(bit_c_0)
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begin
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is_control <= 1'b1;
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is_data <= 1'b0;
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end
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end
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else
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begin
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is_control <= 1'b0;
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is_data <= 1'b1;
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end
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end
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//
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counter_neg <= counter_neg + 5'd1;
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always@(posedge negedge_clk or negedge rx_resetn or posedge last_was_control)
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end
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else
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begin
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begin
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if(!rx_resetn | last_was_control )
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if(is_control)
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begin
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begin
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counter_neg <= 5'd0;
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if(counter_neg == 5'd2)
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begin
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counter_neg <= 5'd1;
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is_control <= 1'b0;
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end
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end
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else
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else
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counter_neg <= counter_neg + 5'd1;
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end
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else if(is_data)
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begin
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begin
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if(counter == 5'd4 & control[2:2])
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if(counter_neg == 5'd5)
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begin
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begin
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counter_neg <= 5'd0;
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counter_neg <= 5'd1;
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is_data <= 1'b0;
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end
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end
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else if(counter == 5'd9)
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else
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begin
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= 5'd0;
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end
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end
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else
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else
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begin
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begin
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counter_neg <= counter_neg + 5'd1;
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counter_neg <= counter_neg + 5'd1;
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end
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end
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end
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end
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end
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end
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end
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//parity error
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always@(*)
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always@(*)
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begin
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begin
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parity_error = 1'b0;
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parity_error = 1'b0;
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if(control_found && last_was_control)
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if(last_is_control)
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begin
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begin
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if(!(control_l_a[2]^control_l_r[0]^control_l_r[1]) != control_l_a[3])
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if(last_was_control)
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begin
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begin
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parity_error = 1'b1;
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if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])
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end
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end
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else if(control_found && last_was_data)
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begin
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if(!(data_l_a[8]^control_l_r[0]^control_l_r[1]) != data_l_a[9])
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begin
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begin
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parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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else if(control_found && last_was_time_code)
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else if(last_was_timec)
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begin
|
begin
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if(!(timecode_l_a[8]^control_l_r[0]^control_l_r[1]) != timecode_l_a[9])
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if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])
|
begin
|
begin
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parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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else if(data_found && last_was_control)
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else if(last_was_data)
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begin
|
begin
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if(!(control_l_a[2]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != control_l_a[3])
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if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])
|
begin
|
begin
|
parity_error = 1'b1;
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parity_error = 1'b1;
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end
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end
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end
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end
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else if(data_found && last_was_data)
|
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begin
|
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if(!(data_l_a[8]^data_l_r[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4])^data_l_r[5]^data_l_r[6]^data_l_r[7] != data_l_a[9])
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begin
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parity_error = 1'b1;
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end
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end
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end
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else if(last_is_data)
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else if(data_found && last_was_time_code)
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begin
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if(!(data_l_r[8]^timecode_l_a[0]^timecode_l_a[1]^timecode_l_a[2]^timecode_l_a[3]^timecode_l_a[4]^timecode_l_a[5]^timecode_l_a[6]^timecode_l_a[7]) != data_l_r[9])
|
|
begin
|
begin
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parity_error = 1'b1;
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if(last_was_control)
|
end
|
|
end
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|
else if(time_code_found && last_was_data)
|
|
begin
|
begin
|
if(!(timecode_l_r[8]^data_l_a[0]^data_l_a[1]^data_l_a[2]^data_l_a[3]^data_l_a[4])^data_l_a[5]^data_l_a[6]^data_l_a[7] != timecode_l_r[9])
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if(!(data[8]^control[1]^control[0]) != data[9])
|
begin
|
begin
|
parity_error = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
end
|
end
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else if(time_code_found && last_was_control)
|
else if(last_was_timec)
|
begin
|
begin
|
if(!(control_l_a[2]^timecode_l_r[0]^timecode_l_r[1]^timecode_l_r[2]^timecode_l_r[3]^timecode_l_r[4]^timecode_l_r[5]^timecode_l_r[6]^timecode_l_r[7]) != control_l_a[3])
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if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])
|
begin
|
begin
|
parity_error = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
else if(last_was_data)
|
|
|
//
|
|
always@(*)
|
|
begin
|
begin
|
|
if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])
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last_was_control = 1'b0;
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last_was_data = 1'b0;
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last_was_time_code= 1'b0;
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|
|
|
if(counter == 5'd4 & control[2:2])
|
|
begin
|
begin
|
last_was_control = 1'b1;
|
parity_error = 1'b1;
|
end
|
end
|
else if(counter == 5'd9 && !control_l_a[2:2] && data_l_a[2:0] != 3'd7)
|
|
begin
|
|
last_was_data = 1'b1;
|
|
end
|
end
|
else if(counter == 5'd9 && control_l_a[2:0] == 3'd7)
|
|
begin
|
|
last_was_time_code= 1'b1;
|
|
end
|
end
|
|
|
end
|
end
|
|
|
//
|
always@(posedge check_c_d or negedge rx_resetn )
|
always@(posedge data_control_up or negedge rx_resetn)
|
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control_found <= 1'b0;
|
control <= 4'd0;
|
data_found <= 1'b0;
|
control_l_r <= 4'd0;
|
time_code_found <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
control_found <= last_was_control;
|
|
data_found <= last_was_data;
|
|
time_code_found <= last_was_time_code;
|
|
end
|
|
|
|
end
|
data <= 10'd0;
|
|
data_l_r <= 10'd0;
|
|
|
//
|
timecode <= 10'd0;
|
always@(posedge last_was_control or negedge rx_resetn)
|
|
begin
|
last_is_control <=1'b0;
|
if(!rx_resetn)
|
last_is_data <=1'b0;
|
begin
|
last_is_timec <=1'b0;
|
control_l_a <= 4'd4;
|
|
control_l_r <= 3'd4;
|
last_was_control <=1'b0;
|
end
|
last_was_data <=1'b0;
|
else
|
last_was_timec <=1'b0;
|
begin
|
|
control_l_a <= control;
|
|
control_l_r <= control_l_a[2:0];
|
|
end
|
|
end
|
|
|
|
always@(posedge last_was_data or negedge rx_resetn)
|
|
begin
|
|
if(!rx_resetn)
|
|
begin
|
|
data_l_a <= 10'd0;
|
|
data_l_r <= 10'd0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
data_l_a <= data;
|
if((control[2:0] != 3'd7 & is_data) == 1'b1)
|
data_l_r <= data_l_a;
|
|
end
|
|
end
|
|
|
|
always@(posedge last_was_time_code or negedge rx_resetn)
|
|
begin
|
|
if(!rx_resetn)
|
|
begin
|
begin
|
timecode_l_a <= 10'd0;
|
|
timecode_l_r <= 10'd0;
|
data <= {bit_d_9,bit_d_8,bit_d_7,bit_d_6,bit_d_5,bit_d_4,bit_d_3,bit_d_2,bit_d_1,bit_d_0};
|
|
data_l_r <= data;
|
|
|
|
last_is_control <=1'b0;
|
|
last_is_data <=1'b1;
|
|
last_is_timec <=1'b0;
|
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
|
end
|
|
else if((control[2:0] == 3'd7 & is_data) == 1'b1)
|
|
begin
|
|
|
|
timecode <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
|
|
|
last_is_control <= 1'b0;
|
|
last_is_data <= 1'b0;
|
|
last_is_timec <= 1'b1;
|
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
|
end
|
|
else if({bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd6 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd13 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd5 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd15 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd7 | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd4 | | {bit_c_3,bit_c_2,bit_c_1,bit_c_0} == 4'd12)
|
|
begin
|
|
|
|
control <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
|
control_l_r <= control[3:0];
|
|
|
|
/*
|
|
if(last_is_data & last_was_data)
|
|
begin
|
|
data <= 10'd0;
|
|
data_l_r <= 10'd0;
|
|
timecode <= 10'd0;
|
|
end
|
|
*/
|
|
last_is_control <= 1'b1;
|
|
last_is_data <= 1'b0;
|
|
last_is_timec <= 1'b0;
|
|
last_was_control <= last_is_control;
|
|
last_was_data <= last_is_data ;
|
|
last_was_timec <= last_is_timec;
|
end
|
end
|
else
|
|
begin
|
|
timecode_l_a <= timecode;
|
|
timecode_l_r <= timecode_l_a;
|
|
end
|
end
|
end
|
end
|
|
|
|
|
endmodule
|
endmodule
|
|
|
