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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Diff between revs 25 and 33

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Rev 25	Rev 33
Line 39...	Line 39...

`input rx_resetn,`	`input rx_resetn,`

`output reg rx_error,`	`output reg rx_error,`

`output rx_got_bit,`	`output reg rx_got_bit,`
`output reg rx_got_null,`	`output reg rx_got_null,`
`output reg rx_got_nchar,`	`output reg rx_got_nchar,`
`output reg rx_got_time_code,`	`output reg rx_got_time_code,`
`output reg rx_got_fct,`	`output reg rx_got_fct,`
`output reg rx_got_fct_fsm,`	`output reg rx_got_fct_fsm,`
Line 54...	Line 54...
`output [7:0] rx_time_out,`	`output [7:0] rx_time_out,`
`output reg rx_tick_out`	`output reg rx_tick_out`
`);`	`);`


`reg [4:0] counter_neg;`	`reg [5:0] counter_neg;`
`reg control_bit_found;`	`reg control_bit_found;`
	`reg data_bit_found;`

`wire posedge_clk;`	`wire posedge_clk;`
`wire negedge_clk;`	`wire negedge_clk;`

`reg bit_c_0;//N`	`reg bit_c_0;//N`
`reg bit_c_1;//P`	`reg bit_c_1;//P`
`reg bit_c_2;//N`	`reg bit_c_2;//N`
`reg bit_c_3;//P`	`reg bit_c_3;//P`
`reg bit_c_ex;//P`

`reg bit_d_0;//N`	`reg bit_d_0;//N`
`reg bit_d_1;//P`	`reg bit_d_1;//P`
`reg bit_d_2;//N`	`reg bit_d_2;//N`
`reg bit_d_3;//P`	`reg bit_d_3;//P`
Line 78...	Line 78...
`reg bit_d_7;//P`	`reg bit_d_7;//P`
`reg bit_d_8;//N`	`reg bit_d_8;//N`
`reg bit_d_9;//P`	`reg bit_d_9;//P`

`reg is_control;`	`reg is_control;`
`reg is_data;`	`//reg is_data;`

`reg last_is_control;`	`reg last_is_control;`
`reg last_is_data;`	`reg last_is_data;`
`reg last_is_timec;`	`reg last_is_timec;`

Line 90...	Line 90...
`reg last_was_data;`	`reg last_was_data;`
`reg last_was_timec;`	`reg last_was_timec;`

`reg [3:0] control;`	`reg [3:0] control;`
`reg [3:0] control_r;`	`reg [3:0] control_r;`
	`reg [3:0] control_p_r;`
`reg [9:0] data;`	`reg [9:0] data;`
`reg [9:0] timecode;`	`reg [9:0] timecode;`

`reg [3:0] control_l_r;`	`reg [3:0] control_l_r;`
`reg [9:0] data_l_r;`	`reg [9:0] data_l_r;`

`reg [9:0] dta_timec;`	`reg [9:0] dta_timec;`
	`reg [9:0] dta_timec_p;`

`reg rx_data_take;`	`reg rx_data_take;`
`reg rx_data_take_0;`	`reg rx_data_take_0;`

`reg first_time;`	`reg ready_control;`
	`reg ready_data;`

`wire ready_control;`	`reg ready_control_p;`
`wire ready_data;`	`reg ready_data_p;`

`//CLOCK RECOVERY`	`reg ready_control_p_r;`
`assign posedge_clk = (rx_din ^ rx_sin)?1'b1:1'b0;`	`reg ready_data_p_r;`
`assign negedge_clk = (!first_time)?1'b0:(!(rx_din ^ rx_sin))?1'b1:1'b0;`
	`reg posedge_p;`

`assign rx_got_bit = (posedge_clk)?1'b1:1'b0;`	`//CLOCK RECOVERY`
	`assign posedge_clk = posedge_p;`
	`assign negedge_clk = !posedge_p;`

`assign rx_time_out = timecode[7:0];`	`assign rx_time_out = timecode[7:0];`

`assign ready_control = is_control;`	`always@(*)`
`assign ready_data = (counter_neg == 5'd5)?is_data:1'b0;`	`begin`

	`rx_got_bit = 1'b0;`

	`if(rx_din \| rx_sin)`
	`begin`
	`rx_got_bit = 1'b1;`
	`end`
	`end`

	`always@(*)`
	`begin`
	`ready_control = 1'b0;`
	`ready_data = 1'b0;`

	`if(counter_neg[5:0] == 6'd4 && !posedge_p)`
	`begin`
	`ready_control = 1'b1;`
	`end`
	`else if(counter_neg[5:0] == 6'd32 && !posedge_p)`
	`begin`
	`ready_data = 1'b1;`
	`end`
	`end`


	`always@(*)`
	`begin`
	`ready_control_p = 1'b0;`
	`ready_data_p = 1'b0;`

	`if(counter_neg[5:0] == 6'd4 && posedge_p)`
	`begin`
	`ready_control_p = 1'b1;`
	`end`
	`else if(counter_neg[5:0] == 6'd32 && posedge_p)`
	`begin`
	`ready_data_p = 1'b1;`
	`end`
	`end`

	`always@(*)`
	`begin`
	`posedge_p = 1'b0;`

	`if((rx_din ^ rx_sin) == 1'b1)`
	`begin`
	`posedge_p = 1'b1;`
	`end`
	`else`
	`begin`
	`posedge_p = 1'b0;`
	`end`
	`end`

`always@(posedge posedge_clk or negedge rx_resetn)`	`always@(posedge posedge_clk or negedge rx_resetn)`
`begin`	`begin`

`if(!rx_resetn)`	`if(!rx_resetn)`
Line 127...	Line 186...
`bit_d_1 <= 1'b0;`	`bit_d_1 <= 1'b0;`
`bit_d_3 <= 1'b0;`	`bit_d_3 <= 1'b0;`
`bit_d_5 <= 1'b0;`	`bit_d_5 <= 1'b0;`
`bit_d_7 <= 1'b0;`	`bit_d_7 <= 1'b0;`
`bit_d_9 <= 1'b0;`	`bit_d_9 <= 1'b0;`
`first_time <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`bit_d_1 <= rx_din;`	`bit_d_1 <= rx_din;`
`bit_d_3 <= bit_d_1;`	`bit_d_3 <= bit_d_1;`
`bit_d_5 <= bit_d_3;`	`bit_d_5 <= bit_d_3;`
`bit_d_7 <= bit_d_5;`	`bit_d_7 <= bit_d_5;`
`bit_d_9 <= bit_d_7;`	`bit_d_9 <= bit_d_7;`
`first_time <= 1'b1;`
`end`	`end`

`end`	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
Line 170...	Line 227...

`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`bit_c_1 <= 1'b0;`	`bit_c_1 <= 1'b0;`
`bit_c_3 <= 1'b0;`	`bit_c_3 <= 1'b0;`
`bit_c_ex <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`bit_c_1 <= rx_din;`	`bit_c_1 <= rx_din;`
`bit_c_3 <= bit_c_1;`	`bit_c_3 <= bit_c_1;`
`bit_c_ex <= bit_c_3;`
`end`	`end`

`end`	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
Line 196...	Line 251...
`bit_c_0 <= rx_din;`	`bit_c_0 <= rx_din;`
`bit_c_2 <= bit_c_0;`	`bit_c_2 <= bit_c_0;`
`end`	`end`
`end`	`end`


`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
`begin`	`begin`

`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`is_control <= 1'b0;`	`rx_got_fct <= 1'b0;`
`is_data <= 1'b0;`
`control_bit_found <= 1'b0;`
`counter_neg <= 5'd0;`
`end`
`else`
`begin`
`if(counter_neg == 5'd0)`
`begin`
`control_bit_found <= rx_din;`
`is_control <= 1'b0;`
`is_data <= 1'b0;`
`counter_neg <= counter_neg + 5'd1;`
`end`
`else if(counter_neg == 5'd1 && control_bit_found)`
`begin`
`is_control <= 1'b1;`
`is_data <= 1'b0;`
`counter_neg <= counter_neg + 5'd1;`
`end`
`else if(counter_neg == 5'd1 && !control_bit_found)`
`begin`
`is_control <= 1'b0;`
`is_data <= 1'b1;`
`counter_neg <= counter_neg + 5'd1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
	`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))`
`if(is_control)`
`begin`


`if(counter_neg == 5'd2)`
`begin`
`control_bit_found <= rx_din;`

`counter_neg <= 5'd1;`
`is_control <= 1'b0;`
`is_data <= 1'b0;`
`end`
`end`
`else if(is_data)`
`begin`
`if(counter_neg == 5'd5)`
`begin`	`begin`
`control_bit_found <= rx_din;`	`rx_got_fct <= 1'b1;`

`counter_neg <= 5'd1;`
`is_data <= 1'b0;`
`is_control <= 1'b0;`
`end`	`end`
`else`	`else`
`counter_neg <= counter_neg + 5'd1;`
`end`
`end`

`end`
`end`

`always@(*)`
`begin`	`begin`
	`rx_got_fct <= 1'b0;`
`rx_got_fct = 1'b0;`

`if(negedge_clk)`
`begin`
`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && ready_control)`
`begin`
`rx_got_fct = 1'b1;`
`end`	`end`
`end`	`end`

`end`	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
`begin`	`begin`

Line 287...	Line 281...
`begin`	`begin`
`rx_error <= 1'b0;`	`rx_error <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(last_is_control)`	`if(last_is_control == 1'b1)`
`begin`	`begin`
`if(last_was_control)`	`if(last_was_control == 1'b1)`
`begin`	`begin`
`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`	`if(!(control[2]^control_l_r[0]^control_l_r[1]) != control[3])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
`end`	`end`
`else if(last_was_timec)`	`end`
	`else if(last_was_timec == 1'b1)`
`begin`	`begin`
`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`	`if(!(control[2]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != control[3])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
	`end`
`end`	`end`
`else if(last_was_data)`	`else if(last_was_data == 1'b1)`
`begin`	`begin`
`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`	`if(!(control[2]^data[0]^data[1]^data[2]^data[3]^data[4]^data[5]^data[6]^data[7]) != control[3])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
	`end`
`end`	`end`

`end`	`end`
`else if(last_is_data)`	`else if(last_is_data == 1'b1)`
`begin`	`begin`
`if(last_was_control)`	`if(last_was_control == 1'b1)`
`begin`	`begin`
`if(!(data[8]^control[1]^control[0]) != data[9])`	`if(!(data[8]^control[1]^control[0]) != data[9])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
	`end`
`end`	`end`
`else if(last_was_timec)`	`else if(last_was_timec == 1'b1)`
`begin`	`begin`
`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`	`if(!(data[8]^timecode[0]^timecode[1]^timecode[2]^timecode[3]^timecode[4]^timecode[5]^timecode[6]^timecode[7]) != data[9])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
	`end`
`end`	`end`
`else if(last_was_data)`	`else if(last_was_data == 1'b1)`
`begin`	`begin`
`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`	`if(!(data[8]^data[0]^data_l_r[1]^data_l_r[2]^data_l_r[3]^data_l_r[4]^data_l_r[5]^data_l_r[6]^data_l_r[7]) != data[9])`
`begin`	`begin`
`rx_error <= 1'b1;`	`rx_error <= 1'b1;`
`end`	`end`
	`else`
	`begin`
	`rx_error <= 1'b0;`
	`end`
`end`	`end`
`end`	`end`

`end`	`end`
`end`	`end`
Line 351...	Line 369...
`rx_got_nchar <= 1'b0;`	`rx_got_nchar <= 1'b0;`
`rx_got_time_code <= 1'b0;`	`rx_got_time_code <= 1'b0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(control[2:0] != 3'd7 && last_is_data )`	`if(last_is_data == 1'b1 )`
`begin`	`begin`
`rx_got_nchar <= 1'b1;`	`rx_got_nchar <= 1'b1;`
`end`	`end`
`else if(control[2:0] == 3'd7 && last_is_data)`	`else if(last_is_timec == 1'b1)`
`begin`	`begin`
`rx_got_time_code <= 1'b1;`	`rx_got_time_code <= 1'b1;`
`end`	`end`
`else if(control_l_r[2:0] == 3'd7 && control[2:0] == 3'd4 && last_is_control)`	`else if(last_is_control == 1'b1)`
`begin`	`begin`
`rx_got_null <= 1'b1;`	`rx_got_null <= 1'b1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`rx_got_null <= rx_got_null;`	`rx_got_null <= 1'b0;`
`rx_got_time_code <= rx_got_time_code;`	`rx_got_nchar <= 1'b0;`
`rx_got_nchar <= rx_got_nchar;`	`rx_got_time_code <= 1'b0;`
`end`	`end`
`end`	`end`
`end`	`end`

`always@(posedge negedge_clk or negedge rx_resetn)`	`always@(posedge negedge_clk or negedge rx_resetn)`
Line 379...	Line 397...
`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`rx_got_fct_fsm <= 1'b0;`	`rx_got_fct_fsm <= 1'b0;`
`rx_buffer_write <= 1'b0;`	`rx_buffer_write <= 1'b0;`
`rx_data_take_0 <= 1'b0;`	`rx_data_take_0 <= 1'b0;`
	`ready_control_p_r <= 1'b0;`
	`ready_data_p_r <= 1'b0;`

`end`	`end`
`else`	`else`
`begin`	`begin`
`rx_data_take_0 <= rx_data_take;`	`rx_data_take_0 <= rx_data_take;`
`rx_buffer_write <= rx_data_take_0;`	`rx_buffer_write <= rx_data_take_0;`

`if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control)`
	`if(ready_control \|\| ready_control_p)`
	`begin`
	`if(is_control)`
	`ready_control_p_r <= 1'b1;`
	`end`
	`else`
	`begin`
	`ready_control_p_r <= 1'b0;`
	`end`

	`if(ready_data \|\| ready_data_p)`
	`begin`
	`if(!is_control)`
	`ready_data_p_r <= 1'b1;`
	`end`
	`else`
	`begin`
	`ready_data_p_r <= 1'b0;`
	`end`

	`if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)`
`rx_got_fct_fsm <= 1'b1;`	`rx_got_fct_fsm <= 1'b1;`
`else`	`else`
`rx_got_fct_fsm <= rx_got_fct_fsm;`	`rx_got_fct_fsm <= rx_got_fct_fsm;`
`end`	`end`
`end`	`end`
Line 400...	Line 442...
`begin`	`begin`
`control_r <= 4'd0;`	`control_r <= 4'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(counter_neg == 5'd2)`	`//if(is_control)`
`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`	`control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};`
`else if(counter_neg == 5'd1 && control == 4'd7)`	`end`
`control_r <= {bit_c_ex,bit_c_2,bit_c_3,bit_c_0};`	`end`

	`always@(posedge ready_control_p or negedge rx_resetn )`
	`begin`
	`if(!rx_resetn)`
	`begin`
	`control_p_r <= 4'd0;`
	`end`
`else`	`else`
`control_r <= control_r;`	`begin`
	`//if(is_control)`
	`control_p_r <= control_r;`
`end`	`end`
`end`	`end`



`always@(posedge ready_data or negedge rx_resetn )`	`always@(posedge ready_data or negedge rx_resetn )`
`begin`	`begin`
`if(!rx_resetn)`	`if(!rx_resetn)`
`begin`	`begin`
`dta_timec <= 10'd0;`	`dta_timec <= 10'd0;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`if(counter_neg == 5'd5)`	`//if(!is_control)`
`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`	`dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};`
	`end`
	`end`


	`always@(posedge ready_data_p or negedge rx_resetn )`
	`begin`
	`if(!rx_resetn)`
	`begin`
	`dta_timec_p <= 10'd0;`
	`end`
	`else`
	`begin`
	`//if(!is_control)`
	`dta_timec_p <= dta_timec;`
	`end`
	`end`

	`always@(posedge negedge_clk or negedge rx_resetn)`
	`begin`

	`if(!rx_resetn)`
	`begin`
	`is_control <= 1'b0;`
	`control_bit_found <= 1'b0;`
	`counter_neg[5:0] <= 6'd1;`
	`end`
`else`	`else`
`dta_timec <= dta_timec;`	`begin`

	`control_bit_found <= rx_din;`

	`case(counter_neg)`
	`6'd1:`
	`begin`
	`counter_neg[5:0] <= 6'd2;`
	`end`
	`6'd2:`
	`begin`
	`if(control_bit_found == 1'b1)`
	`begin`
	`is_control <= 1'b1;`
	`end`
	`else`
	`begin`
	`is_control <= 1'b0;`
	`end`

	`counter_neg[5:0] <= 6'd4;`
	`end`
	`6'd4:`
	`begin`
	`if(is_control == 1'b1)`
	`begin`
	`counter_neg[5:0] <= 6'd2;`
	`is_control <= 1'b0;`
	`end`
	`else`
	`begin`
	`counter_neg[5:0] <= 6'd8;`
	`end`
	`end`
	`6'd8:`
	`begin`
	`counter_neg[5:0] <= 6'd16;`
	`end`
	`6'd16:`
	`begin`
	`counter_neg[5:0] <= 6'd32;`
	`end`
	`6'd32:`
	`begin`
	`is_control <= 1'b0;`
	`counter_neg[5:0] <= 6'd2;`
	`end`
	`default:`
	`begin`
	`is_control <= is_control;`
	`counter_neg[5:0] <= counter_neg[5:0];`
	`end`
	`endcase`

`end`	`end`
`end`	`end`

`always@(posedge posedge_clk or negedge rx_resetn )`	`always@(posedge posedge_clk or negedge rx_resetn )`
`begin`	`begin`
Line 454...	Line 585...

`end`	`end`
`else`	`else`
`begin`	`begin`

`if(ready_control)`	`if(ready_control_p_r)`
`begin`	`begin`
`control <= control_r;`	`control <= control_p_r;`
`control_l_r <= control;`	`control_l_r <= control;`

`last_is_control <= 1'b1;`	`last_is_control <= 1'b1;`
`last_is_data <= 1'b0;`	`last_is_data <= 1'b0;`
`last_is_timec <= 1'b0;`	`last_is_timec <= 1'b0;`
`last_was_control <= last_is_control;`	`last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`last_was_data <= last_is_data ;`
`last_was_timec <= last_is_timec;`	`last_was_timec <= last_is_timec;`
`end`	`end`
`else if(ready_data)`	`else if(ready_data_p_r)`
`begin`	`begin`

`if(control[2:0] != 3'd7)`	`if(control[2:0] != 3'd7)`
`begin`	`begin`
`rx_data_flag <= dta_timec[8:0];`	`rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};`
`data <= dta_timec;`	`data <= dta_timec_p;`
	`data_l_r <= data;`
`last_is_control <=1'b0;`	`last_is_control <=1'b0;`
`last_is_data <=1'b1;`	`last_is_data <=1'b1;`
`last_is_timec <=1'b0;`	`last_is_timec <=1'b0;`
`last_was_control <= last_is_control;`	`last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`last_was_data <= last_is_data ;`
Line 491...	Line 623...
`last_was_control <= last_is_control;`	`last_was_control <= last_is_control;`
`last_was_data <= last_is_data ;`	`last_was_data <= last_is_data ;`
`last_was_timec <= last_is_timec;`	`last_was_timec <= last_is_timec;`
`end`	`end`
`end`	`end`
`else if(last_is_timec)`	`else if(last_is_timec == 1'b1)`
`begin`	`begin`
	`rx_data_take <= 1'b0;`
`data_l_r <= data;`	`rx_tick_out <= 1'b1;`

`rx_data_take <= 1'b1;`
`rx_tick_out <= 1'b0;`

`//meta_hold_setup <= 1'b0;`
`end`	`end`
`else if(last_is_data)`	`else if(last_is_data == 1'b1)`
`begin`	`begin`

`rx_tick_out <= 1'b1;`	`rx_tick_out <= 1'b0;`
`rx_data_take <= 1'b0;`	`rx_data_take <= 1'b1;`

`//meta_hold_setup <= 1'b0;`

`end`	`end`
`else if(last_is_control)`	`else if(last_is_control == 1'b1)`
`begin`	`begin`
`//if(control == 4'd6 \|\| control == 4'd13 \|\| control == 4'd5 \|\| control == 4'd15 \|\| control == 4'd7 \|\| control == 4'd4 \|\| control == 4'd12)`

`if((control[2:0] == 3'd6) == 1'b1 )`	`if(control[2:0] == 3'd6)`
`begin`	`begin`
`data <= 10'b0100000001;`	`rx_data_flag <= 9'd257;`
`rx_data_take <= 1'b1;`	`rx_data_take <= 1'b1;`
`end`	`end`
`else if((control[2:0] == 3'd5) == 1'b1 )`	`else if(control[2:0] == 3'd5)`
`begin`	`begin`
`data <= 10'b0100000000;`	`rx_data_flag <= 9'd256;`
`rx_data_take <= 1'b1;`	`rx_data_take <= 1'b1;`
`end`	`end`
`else`	`else`
`begin`	`begin`
`rx_data_take <= 1'b0;`	`rx_data_take <= 1'b0;`
`end`	`end`

`rx_tick_out <= 1'b0;`	`rx_tick_out <= 1'b0;`

`//meta_hold_setup <= 1'b0;`
`end`	`end`

`end`	`end`
`end`	`end`

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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[/] [spacewiresystemc/] [trunk/] [rtl/] [RTL_VB/] [rx_spw.v] - Diff between revs 25 and 33