//+FHDR------------------------------------------------------------------------
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//+FHDR------------------------------------------------------------------------
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
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//GLADIC Open Source RTL
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//GLADIC Open Source RTL
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//FILE NAME :
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//FILE NAME :
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//DEPARTMENT : IC Design / Verification
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//DEPARTMENT : IC Design / Verification
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR : Felipe Fernandes da Costa
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//AUTHOR’S EMAIL :
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//AUTHOR’S EMAIL :
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//RELEASE HISTORY
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//RELEASE HISTORY
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//VERSION DATE AUTHOR DESCRIPTION
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//VERSION DATE AUTHOR DESCRIPTION
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//1.0 YYYY-MM-DD name
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//1.0 YYYY-MM-DD name
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//KEYWORDS : General file searching keywords, leave blank if none.
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//KEYWORDS : General file searching keywords, leave blank if none.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//PARAMETERS
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//PARAMETERS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//e.g.DATA_WIDTH [32,16] : width of the data : 32:
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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//REUSE ISSUES
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//REUSE ISSUES
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//Reset Strategy :
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//Reset Strategy :
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//Clock Domains :
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//Clock Domains :
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//Critical Timing :
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//Critical Timing :
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//Test Features :
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//Test Features :
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//Asynchronous I/F :
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//Asynchronous I/F :
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//Scan Methodology :
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//Scan Methodology :
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//Instantiations :
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//Instantiations :
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//Synthesizable (y/n) :
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//Synthesizable (y/n) :
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//Other :
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//Other :
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//-FHDR------------------------------------------------------------------------
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//-FHDR------------------------------------------------------------------------
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|
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`timescale 1ns/1ns
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`timescale 1ns/1ns
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|
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module RX_SPW (
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module RX_SPW (
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input rx_din,
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input rx_din,
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input rx_sin,
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input rx_sin,
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|
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input rx_resetn,
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input rx_resetn,
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|
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output rx_error,
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output rx_error,
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|
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output reg rx_got_bit,
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output reg rx_got_bit,
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output reg rx_got_null,
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output reg rx_got_null,
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output reg rx_got_nchar,
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output reg rx_got_nchar,
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output reg rx_got_time_code,
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output reg rx_got_time_code,
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output reg rx_got_fct,
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output reg rx_got_fct,
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output reg rx_got_fct_fsm,
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output reg rx_got_fct_fsm,
|
|
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output reg [8:0] rx_data_flag,
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output reg [8:0] rx_data_flag,
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output reg rx_buffer_write,
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output reg rx_buffer_write,
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|
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output [7:0] rx_time_out,
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output [7:0] rx_time_out,
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output reg rx_tick_out
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output reg rx_tick_out
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);
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);
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|
|
|
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reg [5:0] counter_neg;
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reg [5:0] counter_neg;
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reg control_bit_found;
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reg control_bit_found;
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reg data_bit_found;
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reg data_bit_found;
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|
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wire posedge_clk;
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wire posedge_clk;
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wire negedge_clk;
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wire negedge_clk;
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|
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reg [1:0] state_data_process;
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reg [1:0] state_data_process;
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reg [1:0] next_state_data_process;
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reg [1:0] next_state_data_process;
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|
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reg bit_c_0;//N
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reg bit_c_0;//N
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reg bit_c_1;//P
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reg bit_c_1;//P
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reg bit_c_2;//N
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reg bit_c_2;//N
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reg bit_c_3;//P
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reg bit_c_3;//P
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|
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reg bit_d_0;//N
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reg bit_d_0;//N
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reg bit_d_1;//P
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reg bit_d_1;//P
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reg bit_d_2;//N
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reg bit_d_2;//N
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reg bit_d_3;//P
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reg bit_d_3;//P
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reg bit_d_4;//N
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reg bit_d_4;//N
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reg bit_d_5;//P
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reg bit_d_5;//P
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reg bit_d_6;//N
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reg bit_d_6;//N
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reg bit_d_7;//P
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reg bit_d_7;//P
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reg bit_d_8;//N
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reg bit_d_8;//N
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reg bit_d_9;//P
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reg bit_d_9;//P
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|
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reg is_control;
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reg is_control;
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reg parity_received;
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reg parity_received;
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|
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reg last_is_control;
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reg last_is_control;
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reg last_is_data;
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reg last_is_data;
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reg last_is_timec;
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reg last_is_timec;
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|
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//reg last_was_control;
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//reg last_was_data;
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//reg last_was_timec;
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|
|
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reg [3:0] control;
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reg [3:0] control;
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reg [3:0] control_r;
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reg [3:0] control_r;
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reg [3:0] control_p_r;
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reg [3:0] control_p_r;
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reg [9:0] data;
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reg [9:0] data;
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reg [9:0] timecode;
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reg [9:0] timecode;
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|
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reg [3:0] control_l_r;
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reg [3:0] control_l_r;
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//reg [9:0] data_l_r;
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|
|
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reg [9:0] dta_timec;
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reg [9:0] dta_timec;
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reg [9:0] dta_timec_p;
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reg [9:0] dta_timec_p;
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|
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reg rx_data_take;
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reg rx_data_take_0;
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|
|
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reg rx_got_fct_take;
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reg rx_got_fct_take_0;
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reg rx_got_fct_take_1;
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reg rx_got_fct_take_2;
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reg rx_got_fct_take_3;
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|
|
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reg ready_control;
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reg ready_control;
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reg ready_data;
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reg ready_data;
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|
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reg ready_control_p;
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reg ready_control_p;
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reg ready_data_p;
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reg ready_data_p;
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|
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reg ready_control_p_r;
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reg ready_control_p_r;
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reg ready_data_p_r;
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reg ready_data_p_r;
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|
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reg parity_rec_c;
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reg parity_rec_c;
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reg parity_rec_d;
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reg parity_rec_d;
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|
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reg rx_error_c;
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reg rx_error_c;
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reg rx_error_d;
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reg rx_error_d;
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|
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reg posedge_p;
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reg posedge_p;
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|
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//CLOCK RECOVERY
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//CLOCK RECOVERY
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assign posedge_clk = posedge_p;
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assign posedge_clk = posedge_p;
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assign negedge_clk = !posedge_p;
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assign negedge_clk = !posedge_p;
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|
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assign rx_time_out = timecode[7:0];
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assign rx_time_out = timecode[7:0];
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|
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assign rx_error = rx_error_c | rx_error_d;
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assign rx_error = rx_error_c | rx_error_d;
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|
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always@(*)
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always@(*)
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begin
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begin
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|
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rx_got_bit = 1'b0;
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rx_got_bit = 1'b0;
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|
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if(rx_din | rx_sin)
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if(rx_din | rx_sin)
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begin
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begin
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rx_got_bit = 1'b1;
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rx_got_bit = 1'b1;
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end
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end
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end
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end
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|
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always@(*)
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always@(*)
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begin
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begin
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ready_control = 1'b0;
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ready_control = 1'b0;
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ready_data = 1'b0;
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ready_data = 1'b0;
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|
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if(counter_neg[5:0] == 6'd4 && !posedge_p)
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if(counter_neg[5:0] == 6'd4 && !posedge_p)
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begin
|
begin
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ready_control = 1'b1;
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ready_control = 1'b1;
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end
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end
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else if(counter_neg[5:0] == 6'd32 && !posedge_p)
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else if(counter_neg[5:0] == 6'd32 && !posedge_p)
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begin
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begin
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ready_data = 1'b1;
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ready_data = 1'b1;
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end
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end
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end
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end
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|
|
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always@(*)
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always@(*)
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begin
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begin
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ready_control_p = 1'b0;
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ready_control_p = 1'b0;
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ready_data_p = 1'b0;
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ready_data_p = 1'b0;
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|
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if(counter_neg[5:0] == 6'd4 && posedge_p)
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if(counter_neg[5:0] == 6'd4 && posedge_p)
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begin
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begin
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ready_control_p = 1'b1;
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ready_control_p = 1'b1;
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end
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end
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else if(counter_neg[5:0] == 6'd32 && posedge_p)
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else if(counter_neg[5:0] == 6'd32 && posedge_p)
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begin
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begin
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ready_data_p = 1'b1;
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ready_data_p = 1'b1;
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end
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end
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end
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end
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always@(*)
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always@(*)
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begin
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begin
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posedge_p = 1'b0;
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posedge_p = 1'b0;
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|
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if(rx_din ^ rx_sin)
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if(rx_din ^ rx_sin)
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begin
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begin
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posedge_p = 1'b1;
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posedge_p = 1'b1;
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end
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end
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else
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else
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begin
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begin
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posedge_p = 1'b0;
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posedge_p = 1'b0;
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end
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end
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end
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end
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always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
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begin
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begin
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|
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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bit_d_1 <= 1'b0;
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bit_d_1 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_3 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_5 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_7 <= 1'b0;
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bit_d_9 <= 1'b0;
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bit_d_9 <= 1'b0;
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end
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end
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else
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else
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begin
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begin
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bit_d_1 <= rx_din;
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bit_d_1 <= rx_din;
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bit_d_3 <= bit_d_1;
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bit_d_3 <= bit_d_1;
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bit_d_5 <= bit_d_3;
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bit_d_5 <= bit_d_3;
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bit_d_7 <= bit_d_5;
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bit_d_7 <= bit_d_5;
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bit_d_9 <= bit_d_7;
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bit_d_9 <= bit_d_7;
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end
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end
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end
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end
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
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begin
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begin
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|
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if(!rx_resetn)
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if(!rx_resetn)
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begin
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begin
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bit_d_0 <= 1'b0;
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bit_d_0 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_2 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_4 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_6 <= 1'b0;
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bit_d_8 <= 1'b0;
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bit_d_8 <= 1'b0;
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|
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end
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end
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else
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else
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begin
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begin
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bit_d_0 <= rx_din;
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bit_d_0 <= rx_din;
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bit_d_2 <= bit_d_0;
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bit_d_2 <= bit_d_0;
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bit_d_4 <= bit_d_2;
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bit_d_4 <= bit_d_2;
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bit_d_6 <= bit_d_4;
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bit_d_6 <= bit_d_4;
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bit_d_8 <= bit_d_6;
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bit_d_8 <= bit_d_6;
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end
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end
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end
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end
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always@(posedge posedge_clk or negedge rx_resetn)
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always@(posedge posedge_clk or negedge rx_resetn)
|
begin
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begin
|
|
|
if(!rx_resetn)
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if(!rx_resetn)
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begin
|
begin
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bit_c_1 <= 1'b0;
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bit_c_1 <= 1'b0;
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bit_c_3 <= 1'b0;
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bit_c_3 <= 1'b0;
|
end
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end
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else
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else
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begin
|
begin
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bit_c_1 <= rx_din;
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bit_c_1 <= rx_din;
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bit_c_3 <= bit_c_1;
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bit_c_3 <= bit_c_1;
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end
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end
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|
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end
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end
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|
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always@(posedge negedge_clk or negedge rx_resetn)
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always@(posedge negedge_clk or negedge rx_resetn)
|
begin
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begin
|
|
|
if(!rx_resetn)
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if(!rx_resetn)
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begin
|
begin
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bit_c_0 <= 1'b0;
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bit_c_0 <= 1'b0;
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bit_c_2 <= 1'b0;
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bit_c_2 <= 1'b0;
|
end
|
end
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else
|
else
|
begin
|
begin
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bit_c_0 <= rx_din;
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bit_c_0 <= rx_din;
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bit_c_2 <= bit_c_0;
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bit_c_2 <= bit_c_0;
|
end
|
end
|
end
|
end
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
rx_got_fct <= 1'b0;
|
rx_got_fct <= 1'b0;
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rx_got_fct_take <= 1'b0;
|
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rx_got_fct_take_0 <= 1'b0;
|
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rx_got_fct_take_1 <= 1'b0;
|
|
rx_got_fct_take_2 <= 1'b0;
|
|
rx_got_fct_take_3 <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
|
if(control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && (ready_control_p_r))
|
begin
|
begin
|
rx_got_fct_take <= 1'b1;
|
rx_got_fct <= 1'b1;
|
rx_got_fct_take_0 <= rx_got_fct_take;
|
|
rx_got_fct_take_1 <= rx_got_fct_take_0;
|
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rx_got_fct_take_2 <= rx_got_fct_take_1;
|
|
rx_got_fct_take_3 <= rx_got_fct_take_2;
|
|
rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_got_fct_take <= 1'b0;
|
rx_got_fct <= 1'b0;
|
rx_got_fct_take_0 <= rx_got_fct_take;
|
|
rx_got_fct_take_1 <= rx_got_fct_take_0;
|
|
rx_got_fct_take_2 <= rx_got_fct_take_1;
|
|
rx_got_fct_take_3 <= rx_got_fct_take_2;
|
|
rx_got_fct <= rx_got_fct_take | rx_got_fct_take_0 | rx_got_fct_take_1 | rx_got_fct_take_2 | rx_got_fct_take_3;
|
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
rx_got_null <= 1'b0;
|
rx_got_null <= 1'b0;
|
rx_got_nchar <= 1'b0;
|
rx_got_nchar <= 1'b0;
|
rx_got_time_code <= 1'b0;
|
rx_got_time_code <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if(last_is_data == 1'b1 )
|
if(last_is_data == 1'b1 )
|
begin
|
begin
|
rx_got_nchar <= 1'b1;
|
rx_got_nchar <= 1'b1;
|
end
|
end
|
else if(last_is_timec == 1'b1)
|
else if(last_is_timec == 1'b1)
|
begin
|
begin
|
rx_got_time_code <= 1'b1;
|
rx_got_time_code <= 1'b1;
|
end
|
end
|
else if(last_is_control == 1'b1)
|
else if(last_is_control == 1'b1)
|
begin
|
begin
|
rx_got_null <= 1'b1;
|
rx_got_null <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_got_null <= 1'b0;
|
rx_got_null <= 1'b0;
|
rx_got_nchar <= 1'b0;
|
rx_got_nchar <= 1'b0;
|
rx_got_time_code <= 1'b0;
|
rx_got_time_code <= 1'b0;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
rx_got_fct_fsm <= 1'b0;
|
rx_got_fct_fsm <= 1'b0;
|
rx_buffer_write <= 1'b0;
|
|
rx_data_take_0 <= 1'b0;
|
|
ready_control_p_r <= 1'b0;
|
ready_control_p_r <= 1'b0;
|
ready_data_p_r <= 1'b0;
|
ready_data_p_r <= 1'b0;
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
rx_data_take_0 <= rx_data_take;
|
|
rx_buffer_write <= rx_data_take_0;
|
|
|
|
|
|
if(ready_control || ready_control_p)
|
if(ready_control || ready_control_p)
|
begin
|
begin
|
if(is_control)
|
if(is_control)
|
ready_control_p_r <= 1'b1;
|
ready_control_p_r <= 1'b1;
|
else
|
else
|
ready_control_p_r <= 1'b0;
|
ready_control_p_r <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ready_control_p_r <= 1'b0;
|
ready_control_p_r <= 1'b0;
|
end
|
end
|
|
|
if(ready_data || ready_data_p)
|
if(ready_data || ready_data_p)
|
begin
|
begin
|
if(!is_control)
|
if(!is_control)
|
ready_data_p_r <= 1'b1;
|
ready_data_p_r <= 1'b1;
|
else
|
else
|
ready_data_p_r <= 1'b0;
|
ready_data_p_r <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
ready_data_p_r <= 1'b0;
|
ready_data_p_r <= 1'b0;
|
end
|
end
|
|
|
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
|
if((control_l_r[2:0] != 3'd7 && control[2:0] == 3'd4 && last_is_control == 1'b1 ) == 1'b1)
|
rx_got_fct_fsm <= 1'b1;
|
rx_got_fct_fsm <= 1'b1;
|
else
|
else
|
rx_got_fct_fsm <= rx_got_fct_fsm;
|
rx_got_fct_fsm <= rx_got_fct_fsm;
|
end
|
end
|
end
|
end
|
|
|
always@(posedge ready_control or negedge rx_resetn )
|
always@(posedge ready_control or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control_r <= 4'd0;
|
control_r <= 4'd0;
|
parity_rec_c <= 1'b0;
|
parity_rec_c <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
control_r <= {bit_c_3,bit_c_2,bit_c_1,bit_c_0};
|
parity_rec_c <= bit_c_3;
|
parity_rec_c <= bit_c_3;
|
end
|
end
|
end
|
end
|
|
|
always@(posedge ready_control_p or negedge rx_resetn )
|
always@(posedge ready_control_p or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control_p_r <= 4'd0;
|
control_p_r <= 4'd0;
|
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
control_p_r <= control_r;
|
control_p_r <= control_r;
|
end
|
end
|
end
|
end
|
|
|
|
|
|
|
always@(posedge ready_data or negedge rx_resetn )
|
always@(posedge ready_data or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
dta_timec <= 10'd0;
|
dta_timec <= 10'd0;
|
parity_rec_d <= 1'b0;
|
parity_rec_d <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
dta_timec <= {bit_d_9,bit_d_8,bit_d_0,bit_d_1,bit_d_2,bit_d_3,bit_d_4,bit_d_5,bit_d_6,bit_d_7};
|
parity_rec_d <= bit_d_9;
|
parity_rec_d <= bit_d_9;
|
end
|
end
|
end
|
end
|
|
|
|
|
always@(posedge ready_data_p or negedge rx_resetn )
|
always@(posedge ready_data_p or negedge rx_resetn )
|
begin
|
begin
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
dta_timec_p <= 10'd0;
|
dta_timec_p <= 10'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
dta_timec_p <= dta_timec;
|
dta_timec_p <= dta_timec;
|
end
|
end
|
end
|
end
|
|
|
always@(*)
|
always@(*)
|
begin
|
begin
|
|
|
rx_error_d = 1'b0;
|
rx_error_d = 1'b0;
|
|
|
if(last_is_control && ready_data_p)
|
if(last_is_control && ready_data_p)
|
begin
|
begin
|
if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
|
if(!(dta_timec[8]^control[0]^control[1]) != parity_rec_d)
|
begin
|
begin
|
rx_error_d = 1'b1;
|
rx_error_d = 1'b1;
|
end
|
end
|
end
|
end
|
else if(last_is_data && ready_data_p)
|
else if(last_is_data && ready_data_p)
|
begin
|
begin
|
if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
|
if(!(dta_timec[8]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_d)
|
begin
|
begin
|
rx_error_d = 1'b1;
|
rx_error_d = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(*)
|
always@(*)
|
begin
|
begin
|
|
|
rx_error_c = 1'b0;
|
rx_error_c = 1'b0;
|
|
|
if(last_is_control && ready_control_p)
|
if(last_is_control && ready_control_p)
|
begin
|
begin
|
if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
|
if(!(control_r[2]^control[0]^control[1]) != parity_rec_c)
|
begin
|
begin
|
rx_error_c = 1'b1;
|
rx_error_c = 1'b1;
|
end
|
end
|
end
|
end
|
else if(last_is_data && ready_control_p)
|
else if(last_is_data && ready_control_p)
|
begin
|
begin
|
if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
|
if(!(control_r[2]^data[7]^data[6]^data[5]^data[4]^data[3]^data[2]^data[1]^data[0]) != parity_rec_c)
|
begin
|
begin
|
rx_error_c = 1'b1;
|
rx_error_c = 1'b1;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
always@(posedge negedge_clk or negedge rx_resetn)
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
|
rx_buffer_write <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
end
|
|
else
|
|
begin
|
|
|
|
if(!ready_control_p_r && !ready_data_p_r && !ready_control && !ready_data)
|
|
begin
|
|
if(last_is_timec == 1'b1)
|
|
begin
|
|
rx_tick_out <= 1'b1;
|
|
end
|
|
else if(last_is_data == 1'b1)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
else if(last_is_control == 1'b1)
|
|
begin
|
|
if(control[2:0] == 3'd6)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
else if(control[2:0] == 3'd5)
|
|
begin
|
|
rx_buffer_write <= 1'b1;
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
rx_buffer_write <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
always@(posedge negedge_clk or negedge rx_resetn)
|
|
begin
|
|
|
|
if(!rx_resetn)
|
|
begin
|
is_control <= 1'b0;
|
is_control <= 1'b0;
|
control_bit_found <= 1'b0;
|
control_bit_found <= 1'b0;
|
counter_neg[5:0] <= 6'd1;
|
counter_neg[5:0] <= 6'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
control_bit_found <= rx_din;
|
control_bit_found <= rx_din;
|
|
|
case(counter_neg)
|
case(counter_neg)
|
6'd1:
|
6'd1:
|
begin
|
begin
|
counter_neg[5:0] <= 6'd2;
|
counter_neg[5:0] <= 6'd2;
|
end
|
end
|
6'd2:
|
6'd2:
|
begin
|
begin
|
if(control_bit_found == 1'b1)
|
if(control_bit_found == 1'b1)
|
begin
|
begin
|
is_control <= 1'b1;
|
is_control <= 1'b1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
is_control <= 1'b0;
|
is_control <= 1'b0;
|
end
|
end
|
|
|
counter_neg[5:0] <= 6'd4;
|
counter_neg[5:0] <= 6'd4;
|
end
|
end
|
6'd4:
|
6'd4:
|
begin
|
begin
|
if(is_control == 1'b1)
|
if(is_control == 1'b1)
|
begin
|
begin
|
counter_neg[5:0] <= 6'd2;
|
counter_neg[5:0] <= 6'd2;
|
is_control <= 1'b0;
|
is_control <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
counter_neg[5:0] <= 6'd8;
|
counter_neg[5:0] <= 6'd8;
|
end
|
end
|
end
|
end
|
6'd8:
|
6'd8:
|
begin
|
begin
|
counter_neg[5:0] <= 6'd16;
|
counter_neg[5:0] <= 6'd16;
|
end
|
end
|
6'd16:
|
6'd16:
|
begin
|
begin
|
counter_neg[5:0] <= 6'd32;
|
counter_neg[5:0] <= 6'd32;
|
end
|
end
|
6'd32:
|
6'd32:
|
begin
|
begin
|
is_control <= 1'b0;
|
is_control <= 1'b0;
|
counter_neg[5:0] <= 6'd2;
|
counter_neg[5:0] <= 6'd2;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
is_control <= is_control;
|
is_control <= is_control;
|
counter_neg[5:0] <= counter_neg[5:0];
|
counter_neg[5:0] <= counter_neg[5:0];
|
end
|
end
|
endcase
|
endcase
|
|
|
end
|
end
|
end
|
end
|
|
|
always@(*)
|
always@(*)
|
begin
|
begin
|
|
|
next_state_data_process = state_data_process;
|
next_state_data_process = state_data_process;
|
|
|
case(state_data_process)
|
case(state_data_process)
|
2'd0:
|
2'd0:
|
begin
|
begin
|
if(ready_control_p_r || ready_data_p_r)
|
if(ready_control_p_r || ready_data_p_r)
|
begin
|
begin
|
next_state_data_process = 2'd1;
|
next_state_data_process = 2'd1;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
next_state_data_process = 2'd0;
|
next_state_data_process = 2'd0;
|
end
|
end
|
end
|
end
|
2'd1:
|
2'd1:
|
begin
|
begin
|
next_state_data_process = 2'd0;
|
next_state_data_process = 2'd0;
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
next_state_data_process = 2'd0;
|
next_state_data_process = 2'd0;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
|
|
|
|
always@(posedge negedge_clk or negedge rx_resetn )
|
always@(posedge negedge_clk or negedge rx_resetn )
|
begin
|
begin
|
|
|
if(!rx_resetn)
|
if(!rx_resetn)
|
begin
|
begin
|
control_l_r <= 4'd0;
|
control_l_r <= 4'd0;
|
control <= 4'd0;
|
control <= 4'd0;
|
data <= 10'd0;
|
data <= 10'd0;
|
//data_l_r <= 10'd0;
|
|
|
|
last_is_control <= 1'b0;
|
last_is_control <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b0;
|
last_is_timec <= 1'b0;
|
|
|
//last_was_control <= 1'b0;
|
|
//last_was_data <= 1'b0;
|
|
//last_was_timec <= 1'b0;
|
|
|
|
rx_data_flag <= 9'd0;
|
rx_data_flag <= 9'd0;
|
rx_data_take <= 1'b0;
|
|
|
|
timecode <= 10'd0;
|
timecode <= 10'd0;
|
rx_tick_out <= 1'b0;
|
|
|
|
state_data_process <= 2'd0;
|
state_data_process <= 2'd0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
|
|
state_data_process <= next_state_data_process;
|
state_data_process <= next_state_data_process;
|
|
|
case(state_data_process)
|
case(state_data_process)
|
2'd0:
|
2'd0:
|
begin
|
begin
|
|
|
if(ready_control_p_r)
|
if(ready_control_p_r)
|
begin
|
begin
|
control <= control_p_r;
|
control <= control_p_r;
|
control_l_r <= control;
|
control_l_r <= control;
|
|
|
|
if(control_p_r[2:0] == 3'd6)
|
|
begin
|
|
rx_data_flag <= 9'd257;
|
|
end
|
|
else if(control_p_r[2:0] == 3'd5)
|
|
begin
|
|
rx_data_flag <= 9'd256;
|
|
end
|
|
else
|
|
begin
|
|
rx_data_flag <= rx_data_flag;
|
|
end
|
|
|
last_is_control <= 1'b1;
|
last_is_control <= 1'b1;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b0;
|
last_is_timec <= 1'b0;
|
//last_was_control <= last_is_control;
|
|
//last_was_data <= last_is_data ;
|
|
//last_was_timec <= last_is_timec;
|
|
|
|
rx_data_take <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
|
|
end
|
end
|
else if(ready_data_p_r)
|
else if(ready_data_p_r)
|
begin
|
begin
|
if(control[2:0] != 3'd7)
|
if(control[2:0] != 3'd7)
|
begin
|
begin
|
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
data <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
//data_l_r <= data;
|
rx_data_flag <= {dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
last_is_control <=1'b0;
|
last_is_control <=1'b0;
|
last_is_data <=1'b1;
|
last_is_data <=1'b1;
|
last_is_timec <=1'b0;
|
last_is_timec <=1'b0;
|
//last_was_control <= last_is_control;
|
|
//last_was_data <= last_is_data ;
|
|
//last_was_timec <= last_is_timec;
|
|
end
|
end
|
else if(control[2:0] == 3'd7)
|
else if(control[2:0] == 3'd7)
|
begin
|
begin
|
|
timecode <= {dta_timec_p[9],dta_timec_p[8],dta_timec_p[7],dta_timec_p[6],dta_timec_p[5],dta_timec_p[4],dta_timec_p[3],dta_timec_p[2],dta_timec_p[1],dta_timec_p[0]};
|
last_is_control <= 1'b0;
|
last_is_control <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_data <= 1'b0;
|
last_is_timec <= 1'b1;
|
last_is_timec <= 1'b1;
|
//last_was_control <= last_is_control;
|
|
//last_was_data <= last_is_data ;
|
|
//last_was_timec <= last_is_timec;
|
|
end
|
end
|
|
|
rx_data_take <= 1'b0;
|
|
rx_tick_out <= 1'b0;
|
|
end
|
end
|
else
|
else
|
begin
|
begin
|
timecode <= timecode;
|
timecode <= timecode;
|
end
|
end
|
|
|
end
|
end
|
2'd1:
|
2'd1:
|
begin
|
begin
|
|
|
if(last_is_timec == 1'b1)
|
|
begin
|
|
timecode <= dta_timec;
|
|
rx_tick_out <= 1'b1;
|
|
end
|
|
else if(last_is_data == 1'b1)
|
|
begin
|
|
rx_data_flag <= {data[8],data[7],data[6],data[5],data[4],data[3],data[2],data[1],data[0]};
|
|
rx_data_take <= 1'b1;
|
|
end
|
|
else if(last_is_control == 1'b1)
|
|
begin
|
|
if(control[2:0] == 3'd6)
|
|
begin
|
|
rx_data_flag <= 9'd257;
|
|
rx_data_take <= 1'b1;
|
|
end
|
|
else if(control[2:0] == 3'd5)
|
|
begin
|
|
rx_data_flag <= 9'd256;
|
|
rx_data_take <= 1'b1;
|
|
end
|
|
else
|
|
begin
|
|
rx_data_take <= rx_data_take;
|
|
rx_tick_out <= rx_tick_out;
|
|
end
|
|
|
|
end
|
|
else
|
|
begin
|
|
|
|
rx_data_flag <= rx_data_flag;
|
rx_data_flag <= rx_data_flag;
|
rx_data_take <= rx_data_take;
|
|
|
|
timecode <= timecode;
|
timecode <= timecode;
|
rx_tick_out <= rx_tick_out;
|
|
end
|
|
|
|
end
|
end
|
default:
|
default:
|
begin
|
begin
|
rx_data_flag <= rx_data_flag;
|
rx_data_flag <= rx_data_flag;
|
rx_data_take <= rx_data_take;
|
|
|
|
timecode <= timecode;
|
timecode <= timecode;
|
rx_tick_out <= rx_tick_out;
|
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
