OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [fv/] [alu_chk.e] - Diff between revs 185 and 233

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 185 Rev 233
Line 409... Line 409...
                update_z(dest);
                update_z(dest);
                update_n(dest);
                update_n(dest);
        };
        };
 
 
        exec_sub() is {
        exec_sub() is {
                if (reg_status[3:3] == 1) {
                if (reg_status[3:3] == 1) { // decimal
                        var op1 : int;
                        var op1 : int;
                        var op2 : int;
                        var op2 : int;
 
 
                        warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
                        warning("EXECUTING SBC DECIMAL! IGNORING RESULT!");
 
 
Line 443... Line 443...
                                reg_status[0:0] = 0;
                                reg_status[0:0] = 0;
                        };
                        };
 
 
                        reg_result[3:0] = op1;
                        reg_result[3:0] = op1;
                        reg_result[7:4] = op2;
                        reg_result[7:4] = op2;
 
 
 
                        update_n(reg_result);
 
                        update_z(reg_result);
 
                        update_v(reg_a, inst.alu_a, reg_result);
 
                        reg_a = reg_result;
                }
                }
                else {
                else {
 
                        var temp: int;
 
 
 
                        temp = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        reg_result = reg_a - inst.alu_a - 1 + reg_status[0:0];
                        if (reg_result[7:7] == 1) {
 
                                reg_status[0:0] = 0;
                        reg_status[7:7] = temp[7:7]; // N
                        }
                        print  (reg_a ^ inst.alu_a) & (reg_a ^ temp) & 0x80;
                        else {
                        reg_status[6:6] = (reg_a[7:7] ^ inst.alu_a[7:7]) & (reg_a[7:7] ^ temp[7:7]); // V
                                reg_status[0:0] = 1;
 
                        };
                        if (reg_result == 0) {
 
                                reg_status[1:1] = 1; // Z
 
                        } else {
 
                                reg_status[1:1] = 0; // Z
                };
                };
 
 
                update_z(reg_result);
                        reg_a = temp.as_a(byte);
                update_n(reg_result);
 
                update_v(reg_a, inst.alu_a, reg_result);
 
 
 
 
                        print  (temp & 0xff00);
 
                        print (temp & 0xff00) != 0x0000;
 
 
                reg_a = reg_result;
                        if ( (temp & 0xff00) != 0x0000 ) {
 
                                reg_status[0:0] = 0;
 
                        } else {
 
                                reg_status[0:0] = 1;
 
                        }
 
 
        };
        };
 
        };
 
 
        exec_rot(left : bool, arg1 : byte) is {
        exec_rot(left : bool, arg1 : byte) is {
                var oldcarry : bit;
                var oldcarry : bit;
 
 
                if (left) {
                if (left) {
Line 609... Line 625...
                        update_z(reg_result);
                        update_z(reg_result);
                        update_n(reg_result);
                        update_n(reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        reg_a = reg_result;
                        reg_a = reg_result;
                }
                }
                else {
                else { // stella checked
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
                        reg_result = reg_a + inst.alu_a + reg_status[0:0];
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
                        update_n(reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_v(reg_a, inst.alu_a, reg_result);
                        update_z(reg_result);
                        update_z(reg_result);
                        update_n(reg_result);
                        update_c(reg_a, inst.alu_a, reg_status[0:0]);
 
 
                        reg_a = reg_result;
                        reg_a = reg_result;
                };
                };
        };
        };
 
 
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {
        update_c(arg1 : byte, arg2 : byte, arg3: bit) is {

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.