| Line 12... |
Line 12... |
keep soft PC == 0;
|
keep soft PC == 0;
|
// !SP : uint(bits : 9);
|
// !SP : uint(bits : 9);
|
// keep soft SP == 9'b100000000;
|
// keep soft SP == 9'b100000000;
|
!SP : byte;
|
!SP : byte;
|
keep soft SP == 0;
|
keep soft SP == 0;
|
|
!pointer : byte;
|
|
keep soft pointer == 0;
|
|
|
!more_cycles : bool;
|
!more_cycles : bool;
|
keep soft more_cycles == FALSE;
|
keep soft more_cycles == FALSE;
|
--!R : byte;
|
--!R : byte;
|
-- keep soft R == 0;
|
-- keep soft R == 0;
|
| Line 148... |
Line 150... |
new_state = CYCLE_2;
|
new_state = CYCLE_2;
|
};
|
};
|
CYCLE_2 : {
|
CYCLE_2 : {
|
X = input.alu_x;
|
X = input.alu_x;
|
Y = input.alu_y;
|
Y = input.alu_y;
|
print X, Y;
|
|
outf("CYCLE_1\n");
|
|
case {
|
case {
|
(
|
(
|
instruction == BRK_IMP ||
|
instruction == BRK_IMP ||
|
instruction == PHA_IMP ||
|
instruction == PHA_IMP ||
|
instruction == PHP_IMP ||
|
instruction == PHP_IMP ||
|
| Line 223... |
Line 223... |
instruction == ROR_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == DEC_ZPX ||
|
instruction == DEC_ZPX ||
|
instruction == STA_ZPX ||
|
instruction == STA_ZPX ||
|
instruction == STX_ZPY ||
|
instruction == STX_ZPY ||
|
instruction == STY_ZPX
|
instruction == STY_ZPX ||
|
) : {
|
|
new_state = CYCLE_3;
|
|
PCL = input.data_in;
|
|
--print X, Y;
|
|
--print input.alu_x, input.alu_y;
|
|
--print 't6507lp_fsm.index';
|
|
};
|
|
(
|
|
instruction == LDA_ABX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABY ||
|
instruction == LDA_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDX_ABY ||
|
instruction == LDY_ABX ||
|
instruction == LDY_ABX ||
|
instruction == EOR_ABX ||
|
instruction == EOR_ABX ||
|
| Line 247... |
Line 239... |
instruction == ADC_ABX ||
|
instruction == ADC_ABX ||
|
instruction == ADC_ABY ||
|
instruction == ADC_ABY ||
|
instruction == SBC_ABX ||
|
instruction == SBC_ABX ||
|
instruction == SBC_ABY ||
|
instruction == SBC_ABY ||
|
instruction == CMP_ABX ||
|
instruction == CMP_ABX ||
|
instruction == CMP_ABY
|
instruction == CMP_ABY ||
|
|
instruction == ASL_ABX ||
|
|
instruction == LSR_ABX ||
|
|
instruction == ROL_ABX ||
|
|
instruction == ROR_ABX ||
|
|
instruction == INC_ABX ||
|
|
instruction == DEC_ABX
|
) : {
|
) : {
|
new_state = CYCLE_3;
|
new_state = CYCLE_3;
|
PCL = input.data_in;
|
PCL = input.data_in;
|
--X = input.alu_x;
|
};
|
--Y = input.alu_y;
|
(
|
--print X, Y;
|
instruction == LDA_IDX ||
|
--print input.alu_x, input.alu_y;
|
instruction == STA_IDX ||
|
--print 't6507lp_fsm.index';
|
instruction == ORA_IDX ||
|
--outf("CYCLE_2\n");
|
instruction == EOR_IDX ||
|
|
instruction == AND_IDX ||
|
|
instruction == ADC_IDX ||
|
|
instruction == CMP_IDX ||
|
|
instruction == SBC_IDX
|
|
) : {
|
|
new_state = CYCLE_3;
|
|
pointer = input.data_in;
|
};
|
};
|
(
|
(
|
instruction == TXS_IMP
|
instruction == TXS_IMP
|
) : {
|
) : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
| Line 271... |
Line 276... |
};
|
};
|
};
|
};
|
};
|
};
|
CYCLE_3 : {
|
CYCLE_3 : {
|
case {
|
case {
|
|
//JSR_ABS : {
|
|
// new_state = CYCLE_4;
|
|
// PCH = input.data_in;
|
|
//};
|
(
|
(
|
instruction == BRK_IMP ||
|
instruction == BRK_IMP ||
|
instruction == PLA_IMP ||
|
instruction == PLA_IMP ||
|
instruction == PLP_IMP ||
|
instruction == PLP_IMP ||
|
instruction == RTI_IMP ||
|
instruction == RTI_IMP ||
|
| Line 282... |
Line 291... |
instruction == ASL_ZPG ||
|
instruction == ASL_ZPG ||
|
instruction == LSR_ZPG ||
|
instruction == LSR_ZPG ||
|
instruction == ROL_ZPG ||
|
instruction == ROL_ZPG ||
|
instruction == ROR_ZPG ||
|
instruction == ROR_ZPG ||
|
instruction == INC_ZPG ||
|
instruction == INC_ZPG ||
|
instruction == DEC_ZPG
|
instruction == DEC_ZPG ||
|
) : {
|
|
new_state = CYCLE_4;
|
|
};
|
|
//JSR_ABS : {
|
|
// new_state = CYCLE_4;
|
|
// PCH = input.data_in;
|
|
//};
|
|
(
|
|
instruction == LDA_ZPX ||
|
instruction == LDA_ZPX ||
|
instruction == LDX_ZPY ||
|
instruction == LDX_ZPY ||
|
instruction == LDY_ZPX ||
|
instruction == LDY_ZPX ||
|
instruction == EOR_ZPX ||
|
instruction == EOR_ZPX ||
|
instruction == AND_ZPX ||
|
instruction == AND_ZPX ||
|
| Line 308... |
Line 309... |
instruction == ROR_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == DEC_ZPX ||
|
instruction == DEC_ZPX ||
|
instruction == STA_ZPX ||
|
instruction == STA_ZPX ||
|
instruction == STX_ZPY ||
|
instruction == STX_ZPY ||
|
instruction == STY_ZPX
|
instruction == STY_ZPX ||
|
|
instruction == LDA_IDX ||
|
|
instruction == STA_IDX ||
|
|
instruction == ORA_IDX ||
|
|
instruction == EOR_IDX ||
|
|
instruction == AND_IDX ||
|
|
instruction == ADC_IDX ||
|
|
instruction == CMP_IDX ||
|
|
instruction == SBC_IDX
|
) : {
|
) : {
|
new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
--X = input.alu_x;
|
|
--Y = input.alu_y;
|
|
--print X, Y;
|
|
--print input.alu_x, input.alu_y;
|
|
--print 't6507lp_fsm.index';
|
|
};
|
};
|
(
|
(
|
instruction == ADC_ABS ||
|
instruction == ADC_ABS ||
|
instruction == ASL_ABS ||
|
instruction == ASL_ABS ||
|
instruction == BIT_ABS ||
|
instruction == BIT_ABS ||
|
| Line 352... |
Line 356... |
instruction == ADC_ABX ||
|
instruction == ADC_ABX ||
|
instruction == ADC_ABY ||
|
instruction == ADC_ABY ||
|
instruction == SBC_ABX ||
|
instruction == SBC_ABX ||
|
instruction == SBC_ABY ||
|
instruction == SBC_ABY ||
|
instruction == CMP_ABX ||
|
instruction == CMP_ABX ||
|
instruction == CMP_ABY
|
instruction == CMP_ABY ||
|
|
instruction == ASL_ABX ||
|
|
instruction == LSR_ABX ||
|
|
instruction == ROL_ABX ||
|
|
instruction == ROR_ABX ||
|
|
instruction == INC_ABX ||
|
|
instruction == DEC_ABX
|
) : {
|
) : {
|
new_state = CYCLE_4;
|
new_state = CYCLE_4;
|
PCH = input.data_in;
|
PCH = input.data_in;
|
--X = input.alu_x;
|
|
--Y = input.alu_y;
|
|
--print X, Y;
|
|
--print input.alu_x, input.alu_y;
|
|
--print 't6507lp_fsm.index';
|
|
--outf("CYCLE_3\n");
|
|
};
|
};
|
(
|
(
|
instruction == JMP_ABS
|
instruction == JMP_ABS
|
) : {
|
) : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
| Line 406... |
Line 410... |
instruction == LSR_ZPX ||
|
instruction == LSR_ZPX ||
|
instruction == ROL_ZPX ||
|
instruction == ROL_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == DEC_ZPX ||
|
instruction == DEC_ZPX ||
|
|
instruction == ASL_ABX ||
|
|
instruction == LSR_ABX ||
|
|
instruction == ROL_ABX ||
|
|
instruction == ROR_ABX ||
|
|
instruction == INC_ABX ||
|
|
instruction == DEC_ABX ||
|
(
|
(
|
more_cycles == TRUE &&
|
more_cycles == TRUE &&
|
(
|
(
|
instruction == LDA_ABX ||
|
instruction == LDA_ABX ||
|
instruction == LDA_ABY ||
|
instruction == LDA_ABY ||
|
| Line 428... |
Line 438... |
instruction == CMP_ABX ||
|
instruction == CMP_ABX ||
|
instruction == CMP_ABY
|
instruction == CMP_ABY
|
)
|
)
|
)
|
)
|
) : {
|
) : {
|
--X = input.alu_x;
|
|
--Y = input.alu_y;
|
|
--print X, Y;
|
|
--print input.alu_x, input.alu_y;
|
|
--print 't6507lp_fsm.index';
|
|
--outf("CYCLE_4\n");
|
|
new_state = CYCLE_5;
|
new_state = CYCLE_5;
|
};
|
};
|
|
(
|
|
instruction == LDA_IDX ||
|
|
instruction == STA_IDX ||
|
|
instruction == ORA_IDX ||
|
|
instruction == EOR_IDX ||
|
|
instruction == AND_IDX ||
|
|
instruction == ADC_IDX ||
|
|
instruction == CMP_IDX ||
|
|
instruction == SBC_IDX
|
|
) : {
|
|
new_state = CYCLE_5;
|
|
PCL = input.data_in;
|
|
};
|
default : {
|
default : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
};
|
};
|
};
|
};
|
};
|
};
|
| Line 471... |
Line 488... |
instruction == ASL_ZPX ||
|
instruction == ASL_ZPX ||
|
instruction == LSR_ZPX ||
|
instruction == LSR_ZPX ||
|
instruction == ROL_ZPX ||
|
instruction == ROL_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == ROR_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == INC_ZPX ||
|
instruction == DEC_ZPX
|
instruction == DEC_ZPX ||
|
|
instruction == ASL_ABX ||
|
|
instruction == LSR_ABX ||
|
|
instruction == ROL_ABX ||
|
|
instruction == ROR_ABX ||
|
|
instruction == INC_ABX ||
|
|
instruction == DEC_ABX
|
) : {
|
) : {
|
new_state = CYCLE_6;
|
new_state = CYCLE_6;
|
};
|
};
|
(
|
(
|
instruction == LDA_ABX ||
|
instruction == LDA_IDX ||
|
instruction == LDA_ABY ||
|
instruction == STA_IDX ||
|
instruction == LDX_ABY ||
|
instruction == ORA_IDX ||
|
instruction == LDY_ABX ||
|
instruction == EOR_IDX ||
|
instruction == EOR_ABX ||
|
instruction == AND_IDX ||
|
instruction == EOR_ABY ||
|
instruction == ADC_IDX ||
|
instruction == AND_ABX ||
|
instruction == CMP_IDX ||
|
instruction == AND_ABY ||
|
instruction == SBC_IDX
|
instruction == ORA_ABX ||
|
|
instruction == ORA_ABY ||
|
|
instruction == ADC_ABX ||
|
|
instruction == ADC_ABY ||
|
|
instruction == SBC_ABX ||
|
|
instruction == SBC_ABY ||
|
|
instruction == CMP_ABX ||
|
|
instruction == CMP_ABY
|
|
) : {
|
) : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_6;
|
--X = input.alu_x;
|
PCH = input.data_in;
|
--Y = input.alu_y;
|
|
--print X, Y;
|
|
--print input.alu_x, input.alu_y;
|
|
--print 't6507lp_fsm.index';
|
|
--outf("CYCLE_5\n");
|
|
};
|
};
|
--(
|
|
-- instruction == LDA_ZPX ||
|
|
-- instruction == LDX_ZPY ||
|
|
-- instruction == LDY_ZPX ||
|
|
-- instruction == EOR_ZPX ||
|
|
-- instruction == AND_ZPX ||
|
|
-- instruction == ORA_ZPX ||
|
|
-- instruction == ADC_ZPX ||
|
|
-- instruction == SBC_ZPX ||
|
|
-- instruction == CMP_ZPX ||
|
|
-- instruction == ASL_ZPX ||
|
|
-- instruction == LSR_ZPX ||
|
|
-- instruction == ROL_ZPX ||
|
|
-- instruction == ROR_ZPX ||
|
|
-- instruction == INC_ZPX ||
|
|
-- instruction == DEC_ZPX ||
|
|
-- instruction == STA_ZPX ||
|
|
-- instruction == STX_ZPY ||
|
|
-- instruction == STY_ZPX
|
|
--) : {
|
|
-- new_state = CYCLE_1;
|
|
--X = input.alu_x;
|
|
--Y = input.alu_y;
|
|
--print input.alu_x, input.alu_y;
|
|
|
|
--};
|
|
default : {
|
default : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
};
|
};
|
};
|
};
|
};
|
};
|
| Line 546... |
Line 530... |
instructions == RTI_IMP
|
instructions == RTI_IMP
|
) : {
|
) : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
PCH = input.data_in;
|
PCH = input.data_in;
|
};
|
};
|
|
(
|
|
instruction == ASL_ABX ||
|
|
instruction == LSR_ABX ||
|
|
instruction == ROL_ABX ||
|
|
instruction == ROR_ABX ||
|
|
instruction == INC_ABX ||
|
|
instruction == DEC_ABX
|
|
) : {
|
|
new_state = CYCLE_7;
|
|
};
|
default : {
|
default : {
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
};
|
};
|
};
|
};
|
};
|
};
|
CYCLE_7 : {
|
CYCLE_7 : {
|
//case (instruction) {
|
case (instruction) {
|
// BRK_IMP : {
|
BRK_IMP : {
|
// new_state = CYCLE_6;
|
|
// };
|
|
// default :
|
|
new_state = CYCLE_1;
|
new_state = CYCLE_1;
|
PCH = input.data_in
|
PCH = input.data_in;
|
|
};
|
|
default : {
|
|
new_state = CYCLE_1;
|
|
};
|
|
};
|
};
|
};
|
};
|
};
|
old_input = new_input;
|
old_input = new_input;
|
new_input = input;
|
new_input = input;
|
};
|
};
|
| Line 579... |
Line 575... |
more_cycles = FALSE;
|
more_cycles = FALSE;
|
print_state();
|
print_state();
|
print addr;
|
print addr;
|
last_instruction = instructions;
|
last_instruction = instructions;
|
instructions = instruction;
|
instructions = instruction;
|
//print instructions;
|
|
//print last_instruction;
|
|
if (mem_rw != 0) {
|
if (mem_rw != 0) {
|
dut_error("Mem_rw is Wrong!");
|
dut_error("Mem_rw is Wrong!");
|
};
|
};
|
if (rst == 0) {
|
if (rst == 0) {
|
case {
|
case {
|
| Line 644... |
Line 638... |
last_instruction == ADC_ABX ||
|
last_instruction == ADC_ABX ||
|
last_instruction == ADC_ABY ||
|
last_instruction == ADC_ABY ||
|
last_instruction == SBC_ABX ||
|
last_instruction == SBC_ABX ||
|
last_instruction == SBC_ABY ||
|
last_instruction == SBC_ABY ||
|
last_instruction == CMP_ABX ||
|
last_instruction == CMP_ABX ||
|
last_instruction == CMP_ABY
|
last_instruction == CMP_ABY ||
|
|
last_instruction == LDA_IDX ||
|
|
last_instruction == ORA_IDX ||
|
|
last_instruction == EOR_IDX ||
|
|
last_instruction == AND_IDX ||
|
|
last_instruction == ADC_IDX ||
|
|
last_instruction == CMP_IDX ||
|
|
last_instruction == SBC_IDX
|
) : {
|
) : {
|
if (alu_opcode != last_instruction) {
|
if (alu_opcode != last_instruction) {
|
--print addr[7:0],X + PCL;
|
|
dut_error("alu_opcode is Wrong!");
|
dut_error("alu_opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 1) {
|
if (alu_enable != 1) {
|
dut_error("alu_enable is Wrong!");
|
dut_error("alu_enable is Wrong!");
|
};
|
};
|
if (addr != PC) {
|
if (addr != PC) {
|
dut_error("Address is Wrong!");
|
dut_error("Address is Wrong!");
|
};
|
};
|
};
|
};
|
|
--(
|
|
--) : {
|
|
-- if (alu_opcode != last_instruction) {
|
|
-- dut_error("alu_opcode is Wrong!");
|
|
-- };
|
|
-- if (alu_enable != 1) {
|
|
-- dut_error("alu_enable is Wrong!");
|
|
-- };
|
|
-- if (addr[7:0] != PCL) {
|
|
-- dut_error("Address is Wrong!");
|
|
-- };
|
|
-- if (addr[12:8] != PCH[4:0]) {
|
|
-- dut_error("Address is Wrong!");
|
|
-- };
|
|
--};
|
default : {
|
default : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
--print alu_enable;
|
|
--print alu_opcode;
|
|
--print last_instruction;
|
|
dut_error("alu_opcode is Wrong!");
|
dut_error("alu_opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
dut_error("alu_enable is Wrong!");
|
dut_error("alu_enable is Wrong!");
|
};
|
};
|
| Line 782... |
Line 794... |
instructions == ADC_ABX ||
|
instructions == ADC_ABX ||
|
instructions == ADC_ABY ||
|
instructions == ADC_ABY ||
|
instructions == SBC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == SBC_ABY ||
|
instructions == SBC_ABY ||
|
instructions == CMP_ABX ||
|
instructions == CMP_ABX ||
|
instructions == CMP_ABY
|
instructions == CMP_ABY ||
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX ||
|
|
instructions == LDA_IDX ||
|
|
instructions == STA_IDX ||
|
|
instructions == ORA_IDX ||
|
|
instructions == EOR_IDX ||
|
|
instructions == AND_IDX ||
|
|
instructions == ADC_IDX ||
|
|
instructions == CMP_IDX ||
|
|
instructions == SBC_IDX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 840... |
Line 866... |
instructions == INX_IMP ||
|
instructions == INX_IMP ||
|
instructions == INY_IMP ||
|
instructions == INY_IMP ||
|
instructions == LSR_ACC ||
|
instructions == LSR_ACC ||
|
instructions == PHA_IMP ||
|
instructions == PHA_IMP ||
|
instructions == ROL_ACC ||
|
instructions == ROL_ACC ||
|
|
instructions == ROR_ACC ||
|
instructions == SEC_IMP ||
|
instructions == SEC_IMP ||
|
instructions == SED_IMP ||
|
instructions == SED_IMP ||
|
instructions == SEI_IMP ||
|
instructions == SEI_IMP ||
|
instructions == TAX_IMP ||
|
instructions == TAX_IMP ||
|
instructions == TAY_IMP ||
|
instructions == TAY_IMP ||
|
| Line 1017... |
Line 1044... |
if (addr != PCL) {
|
if (addr != PCL) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == LDA_IDX ||
|
|
instructions == STA_IDX ||
|
|
instructions == ORA_IDX ||
|
|
instructions == EOR_IDX ||
|
|
instructions == AND_IDX ||
|
|
instructions == ADC_IDX ||
|
|
instructions == CMP_IDX ||
|
|
instructions == SBC_IDX
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr != pointer) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
(
|
instructions == ADC_ABS ||
|
instructions == ADC_ABS ||
|
instructions == AND_ABS ||
|
instructions == AND_ABS ||
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == BIT_ABS ||
|
instructions == BIT_ABS ||
|
instructions == CMP_ABS ||
|
instructions == CMP_ABS ||
|
| Line 1043... |
Line 1093... |
instructions == EOR_ABX ||
|
instructions == EOR_ABX ||
|
instructions == AND_ABX ||
|
instructions == AND_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ADC_ABX ||
|
instructions == ADC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == CMP_ABX
|
instructions == CMP_ABX ||
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1231... |
Line 1287... |
};
|
};
|
if (mem_rw != 0) {
|
if (mem_rw != 0) {
|
dut_error("MEM_RW should be 0 (WRITE)");
|
dut_error("MEM_RW should be 0 (WRITE)");
|
};
|
};
|
--TODO: Isn`t it suppose to have ADDRH == 0????
|
--TODO: Isn`t it suppose to have ADDRH == 0????
|
if (addr != PCL + X) {
|
if (PCL + X > 255) {
|
print addr[7:0], PCL+X, PCL, X, 't6507lp_fsm.index';
|
if (addr[7:0] != PCL + X - 256) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
};
|
};
|
(
|
(
|
instructions == LDA_ABX ||
|
instructions == LDA_ABX ||
|
instructions == LDY_ABX ||
|
instructions == LDY_ABX ||
|
instructions == EOR_ABX ||
|
instructions == EOR_ABX ||
|
instructions == AND_ABX ||
|
instructions == AND_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ADC_ABX ||
|
instructions == ADC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == CMP_ABX
|
instructions == CMP_ABX ||
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1258... |
Line 1326... |
dut_error("MEM_RW should be 0 (WRITE)");
|
dut_error("MEM_RW should be 0 (WRITE)");
|
};
|
};
|
if (PCL + X > 255) {
|
if (PCL + X > 255) {
|
more_cycles = TRUE;
|
more_cycles = TRUE;
|
if (addr[7:0] != PCL + X - 256) {
|
if (addr[7:0] != PCL + X - 256) {
|
--print addr[7:0], PCL + X - 256;
|
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
}
|
}
|
else {
|
else {
|
if (addr[7:0] != PCL + X) {
|
if (addr[7:0] != PCL + X) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
};
|
};
|
};
|
};
|
(
|
(
|
|
instructions == LDA_IDX ||
|
|
instructions == STA_IDX ||
|
|
instructions == ORA_IDX ||
|
|
instructions == EOR_IDX ||
|
|
instructions == AND_IDX ||
|
|
instructions == ADC_IDX ||
|
|
instructions == CMP_IDX ||
|
|
instructions == SBC_IDX
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (pointer + X > 255) {
|
|
if (addr[7:0] != pointer + X - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != pointer + X) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
(
|
instructions == LDX_ZPY ||
|
instructions == LDX_ZPY ||
|
instructions == LDA_ABY ||
|
instructions == LDA_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDX_ABY ||
|
instructions == EOR_ABY ||
|
instructions == EOR_ABY ||
|
instructions == AND_ABY ||
|
instructions == AND_ABY ||
|
| Line 1291... |
Line 1388... |
dut_error("MEM_RW should be 0 (WRITE)");
|
dut_error("MEM_RW should be 0 (WRITE)");
|
};
|
};
|
if (PCL + Y > 255) {
|
if (PCL + Y > 255) {
|
more_cycles = TRUE;
|
more_cycles = TRUE;
|
if (addr[7:0] != PCL + Y - 256) {
|
if (addr[7:0] != PCL + Y - 256) {
|
print addr[7:0], PCL + Y - 256;
|
|
print PCL, Y;
|
|
print 't6507lp_fsm.index';
|
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
}
|
}
|
else {
|
else {
|
if (addr[7:0] != PCL + Y) {
|
if (addr[7:0] != PCL + Y) {
|
| Line 1392... |
Line 1486... |
dut_error("ASL_ACC is Wrong!");
|
dut_error("ASL_ACC is Wrong!");
|
};
|
};
|
if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
};
|
};
|
if (addr != PCL + X) {
|
if (PCL + X > 255) {
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
};
|
};
|
|
};
|
(
|
(
|
instructions == STX_ZPY
|
instructions == STX_ZPY
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
| Line 1408... |
Line 1509... |
dut_error("ASL_ACC is Wrong!");
|
dut_error("ASL_ACC is Wrong!");
|
};
|
};
|
if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
dut_error("MEM_RW should be 1 (WRITE)");
|
dut_error("MEM_RW should be 1 (WRITE)");
|
};
|
};
|
if (addr != PCL + Y) {
|
if (PCL + Y > 255) {
|
|
if (addr[7:0] != PCL + Y - 256) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + Y) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
};
|
};
|
(
|
(
|
instructions == PLA_IMP ||
|
instructions == PLA_IMP ||
|
instructions == PLP_IMP
|
instructions == PLP_IMP
|
) : {
|
) : {
|
| Line 1442... |
Line 1550... |
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
dut_error("RTI_IMP is Wrong!");
|
dut_error("RTI_IMP is Wrong!");
|
};
|
};
|
if (addr != SP + 256) {
|
if (addr != SP + 256) {
|
--print addr, SP;
|
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
SP = SP + 1;
|
SP = SP + 1;
|
};
|
};
|
(
|
(
|
| Line 1504... |
Line 1611... |
// dut_error("ADDR should be equal SP!");
|
// dut_error("ADDR should be equal SP!");
|
// };
|
// };
|
// SP = SP - 1;
|
// SP = SP - 1;
|
//};
|
//};
|
(
|
(
|
|
instructions == LDA_IDX ||
|
|
instructions == STA_IDX ||
|
|
instructions == ORA_IDX ||
|
|
instructions == EOR_IDX ||
|
|
instructions == AND_IDX ||
|
|
instructions == ADC_IDX ||
|
|
instructions == CMP_IDX ||
|
|
instructions == SBC_IDX
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (pointer + X + 1 > 255) {
|
|
if (addr[7:0] != pointer + X + 1 - 256) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != pointer + X + 1) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
};
|
|
(
|
instructions == RTI_IMP
|
instructions == RTI_IMP
|
) : {
|
) : {
|
if (alu_opcode != instructions) {
|
if (alu_opcode != instructions) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
| Line 1564... |
Line 1701... |
instructions == EOR_ABX ||
|
instructions == EOR_ABX ||
|
instructions == AND_ABX ||
|
instructions == AND_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ORA_ABX ||
|
instructions == ADC_ABX ||
|
instructions == ADC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == SBC_ABX ||
|
instructions == CMP_ABX
|
instructions == CMP_ABX ||
|
|
(
|
|
more_cycles == TRUE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
)
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
if (alu_enable != 0) {
|
if (alu_enable != 0) {
|
| Line 1583... |
Line 1731... |
if (addr[12:8] != PCH[4:0] + 1) {
|
if (addr[12:8] != PCH[4:0] + 1) {
|
dut_error("ADDR is wrong!");
|
dut_error("ADDR is wrong!");
|
};
|
};
|
};
|
};
|
(
|
(
|
|
more_cycles == FALSE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
};
|
|
(
|
instructions == LDX_ZPY ||
|
instructions == LDX_ZPY ||
|
instructions == LDA_ABY ||
|
instructions == LDA_ABY ||
|
instructions == LDX_ABY ||
|
instructions == LDX_ABY ||
|
instructions == EOR_ABY ||
|
instructions == EOR_ABY ||
|
instructions == AND_ABY ||
|
instructions == AND_ABY ||
|
| Line 1626... |
Line 1798... |
dut_error("ASL_ACC is Wrong!");
|
dut_error("ASL_ACC is Wrong!");
|
};
|
};
|
if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
dut_error("MEM_RW should be 0 (WRITE)");
|
dut_error("MEM_RW should be 0 (WRITE)");
|
};
|
};
|
if (addr != PCL + X) {
|
if (PCL + X > 255) {
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
};
|
};
|
|
};
|
(
|
(
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == DEC_ABS ||
|
instructions == DEC_ABS ||
|
instructions == INC_ABS ||
|
instructions == INC_ABS ||
|
instructions == LSR_ABS ||
|
instructions == LSR_ABS ||
|
| Line 1694... |
Line 1873... |
// };
|
// };
|
// PC [7:0] = PCL;
|
// PC [7:0] = PCL;
|
// PC[12:8] = PCH[4:0];
|
// PC[12:8] = PCH[4:0];
|
//};
|
//};
|
(
|
(
|
|
instructions == LDA_IDX ||
|
|
instructions == ORA_IDX ||
|
|
instructions == EOR_IDX ||
|
|
instructions == AND_IDX ||
|
|
instructions == ADC_IDX ||
|
|
instructions == CMP_IDX ||
|
|
instructions == SBC_IDX
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 0) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
(
|
|
instructions == STA_IDX ||
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR is wrong");
|
|
};
|
|
};
|
|
(
|
instructions == RTI_IMP
|
instructions == RTI_IMP
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
| Line 1744... |
Line 1967... |
dut_error("ASL_ACC is Wrong!");
|
dut_error("ASL_ACC is Wrong!");
|
};
|
};
|
if (mem_rw != 1) {
|
if (mem_rw != 1) {
|
dut_error("MEM_RW should be 0 (WRITE)");
|
dut_error("MEM_RW should be 0 (WRITE)");
|
};
|
};
|
if (addr != PCL + X) {
|
if (PCL + X > 255) {
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR should be equal SP!");
|
|
};
|
|
}
|
|
else {
|
|
if (addr[7:0] != PCL + X) {
|
dut_error("ADDR should be equal SP!");
|
dut_error("ADDR should be equal SP!");
|
};
|
};
|
};
|
};
|
|
};
|
|
(
|
|
more_cycles == TRUE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0] + 1) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
};
|
|
(
|
|
more_cycles == FALSE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
) : {
|
|
if (alu_opcode != instructions) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 1) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
};
|
(
|
(
|
instructions == ASL_ABS ||
|
instructions == ASL_ABS ||
|
instructions == DEC_ABS ||
|
instructions == DEC_ABS ||
|
instructions == INC_ABS ||
|
instructions == INC_ABS ||
|
instructions == LSR_ABS ||
|
instructions == LSR_ABS ||
|
| Line 1779... |
Line 2063... |
CYCLE_7 : {
|
CYCLE_7 : {
|
print_state();
|
print_state();
|
print addr;
|
print addr;
|
case {
|
case {
|
(
|
(
|
|
more_cycles == TRUE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + X - 256) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0] + 1) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
};
|
|
(
|
|
more_cycles == FALSE &&
|
|
(
|
|
instructions == ASL_ABX ||
|
|
instructions == LSR_ABX ||
|
|
instructions == ROL_ABX ||
|
|
instructions == ROR_ABX ||
|
|
instructions == INC_ABX ||
|
|
instructions == DEC_ABX
|
|
)
|
|
) : {
|
|
if (alu_opcode.as_a(byte) != 0) {
|
|
dut_error("Opcode is Wrong!");
|
|
};
|
|
if (alu_enable != 0) {
|
|
dut_error("ASL_ACC is Wrong!");
|
|
};
|
|
if (mem_rw != 1) {
|
|
dut_error("MEM_RW should be 0 (WRITE)");
|
|
};
|
|
if (addr[7:0] != PCL + X) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
if (addr[12:8] != PCH[4:0]) {
|
|
dut_error("ADDR is wrong!");
|
|
};
|
|
};
|
|
(
|
instructions == BRK_IMP
|
instructions == BRK_IMP
|
) : {
|
) : {
|
if (alu_opcode.as_a(byte) != 0) {
|
if (alu_opcode.as_a(byte) != 0) {
|
dut_error("Opcode is Wrong!");
|
dut_error("Opcode is Wrong!");
|
};
|
};
|
